IP Library Granted Patent US 10,038,385
Granted Patent B2
US 10,038,385 · App. 15/471,666 · Granted Jul 31, 2018

Flyback converter and controller using counter and current emulator

Inventors: Lei Chen (Milpitas, CA); Chih-Hsien Hsieh (Changhua County, TW); Yue-Hong Tang (Nantou County, TW)
Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
H02M3/33515H02M1/08H02M3/33523H02M2001/0009
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,038,385
App. No.
15/471,666
Granted
Jul 31, 2018
Kind
B2
Abstract

In one embodiment, a power supply controller, or alternately a semiconductor device having a power supply controller, may have a circuit configured configuring the PWM circuit to form a first signal having a value formed to be representative of a peak value of a primary current through the power switch and having a duration that is representative of a time interval that a secondary current is flowing through a secondary winding wherein the peak value is the peak value during an on-time of the power switch, and configured to form a current having a value that is representative of an average value of the secondary current.

Claims (39)

1. A power supply controller comprising:

a PWM circuit configured to control a power switch to control a primary current through a primary inductor of a transformer to regulate an output voltage formed from a secondary winding of the transformer wherein the secondary winding is configured to be coupled to a synchronous rectifier, the PWM circuit configured to enable the power switch at a frequency having a period;

a first circuit configured to form a sense signal that is representative of an auxiliary voltage from an auxiliary winding of the transformer wherein the sense signal is representative of a value of the output voltage for at least a portion of an off-time of the power switch;

a current circuit configured to form a first current that is representative of a peak value of the primary current that flows through the power switch during an on-time of the power switch during the period;

a timing detection circuit configured to form a timing signal that is representative of at least a portion of a time interval that a secondary current is flowing in the secondary winding during the period; and

a current estimator circuit configured charge a capacitor with the first current for the time interval, the current estimator circuit configured to form a second current to discharge the capacitor during the period and to form an estimated current that is representative of the second current wherein the estimated current is representative of an average value of the secondary current during the period, the current estimator circuit including a comparator configured to compare a voltage on the capacitor to a reference voltage, a counter configured to increment a count of the counter in response to the voltage on the capacitor having a value greater than the reference voltage in response to disabling the power switch or to decrement the count of the counter in response to the voltage on the capacitor having a value no greater than the reference voltage in response to disabling the power switch, wherein the count of the counter adjusts a value of the second current.

2. The power supply controller of claim 1 wherein the current estimator circuit includes a current sinking DAC configured to receive the count of the counter and form the second current responsively to the count of the counter.

3. The power supply controller of claim 1 wherein the timing detection circuit includes a zero crossing detection circuit configured to detect a substantially zero crossing of the secondary current and responsively negate the timing signal.

4. The power supply controller of claim 3 wherein the timing detection circuit is configured to assert the timing signal in response to disabling the power switch.

5. The power supply controller of claim 1 further including a peak detection circuit configured to form a peak signal that is representative of the peak value of the primary current, and wherein the current circuit includes a variable current source configured to form a value of the first current responsively to a value of the peak signal.

6. The power supply controller of claim 5 further including the comparator configured to control counting of the counter responsively to a value of a voltage on the capacitor.

7. A power supply controller comprising:

a PWM circuit configured to control a power switch to control a primary current through a primary inductor of a transformer to regulate an output voltage formed from a secondary winding of the transformer wherein the secondary winding is configured to be coupled to a synchronous rectifier, the PWM circuit configured to enable the power switch at a frequency having a period;

a first circuit configured to form a sense signal that is representative of an auxiliary voltage from an auxiliary winding of the transformer wherein the sense signal is representative of a value of the output voltage for at least a portion of an off-time of the power switch;

a current circuit configured to form a first current that is representative of a peak value of the primary current that flows through the power switch during an on-time of the power switch wherein the current circuit includes a first variable current source configured to form the first current;

a timing detection circuit configured to form a timing signal that is representative of at least a portion of a time interval that a secondary current is flowing in the secondary winding during the period; and

a current estimator circuit configured charge a capacitor with the first current for the time interval, the current estimator circuit configured to form a second current to discharge the capacitor during the period and to form an estimated current that is representative of the second current wherein the estimated current is representative of an average value of the secondary current during the period, the current estimator circuit including a first switch configured to couple the first current to the capacitor for the time interval, and a second current source configured to discharge the capacitor during the period and wherein the current estimator circuit includes a control circuit configured to adjust a value of the second current to maintain a peak value of a voltage on the capacitor to be substantially constant from one period to another period.

8. A semiconductor device having a power supply controller comprising:

a PWM circuit configured to control a power switch to control a primary current through a primary inductor of a transformer to regulate an output voltage formed from a secondary winding of the transformer, the PWM circuit configured to enable the power switch at a frequency having a period;

a first circuit configured to form a sense signal that is representative of a value of the output voltage for at least a portion of an off-time of the power switch;

a current circuit configured to form a first current that is representative of a peak value of a current that flows through the power switch during an on-time of the power switch;

a timing detection circuit configured to form a timing signal that is representative of a time interval that a secondary current is flowing in the secondary winding; and

a current estimator circuit configured to receive the timing signal and the first current, and to form an estimated current signal having a value that is representative of a result of integrating the first current for the time interval, the current estimator circuit configured to charge a capacitor with the first current during the first time interval and to reset the capacitor in response to disabling the power switch.

9. The power supply controller of claim 8 wherein the timing detection circuit is configured to assert the timing signal in response to initiation of the secondary current and to negate the timing signal in response to detecting the secondary current becoming substantially zero.

10. The power supply controller of claim 9 wherein the timing detection circuit includes a zero crossing detection circuit configured to detect the secondary current becoming substantially zero.

11. The power supply controller of claim 9 wherein the timing detection circuit includes a zero crossing detection circuit configured to detect a change in the value of the sense signal subsequently to an increase in the sense signal that occurs responsively to disabling the power switch.

12. The power supply controller of claim 8 wherein the current estimator circuit includes a second circuit configured to form a second current signal during the time interval wherein a value of the second current signal is representative of the peak value of the primary current.

13. The power supply controller of claim 12 wherein the first circuit includes a variable current source configured to form a second current having a value that is representative of the peak value of the primary current, wherein the first circuit includes a switch configured to couple the second current having a value that is representative of the peak value of the primary current to a capacitor for the time interval.

14. A method of forming a semiconductor device comprising:

forming a PWM circuit of the semiconductor device to control a power switch to control a primary current through a primary inductor of a transformer to regulate an output voltage formed from a secondary current that is formed by a secondary winding of the transformer, the PWM circuit configured to enable the power switch at a frequency having a period;

configuring the PWM circuit to form a first signal having a value formed to be representative of a peak value of a primary current through the power switch and having a duration that is representative of a time interval that a secondary current is flowing through the secondary winding wherein the peak value is the peak value during an on-time of the power switch;

configuring the PWM circuit to form a current having a value that is representative of an average value of the secondary current;

configuring a peak detection circuit to form a peak signal that is representative of the peak value of the primary current; and

configuring a current circuit to include a variable current source configured to form a value of the first signal responsively to a value of the peak signal and a comparator configured to control counting of a counter responsively to a value of a voltage on the capacitor.

15. The method of claim 14 wherein configuring the PWM circuit to form the first signal that is representative of the peak value of the primary current includes configuring a peak circuit to form a peak signal that is representative of the peak value of the primary current; and

configuring a current estimator circuit to couple the first signal to a node for the time interval.

16. The method of claim 14 wherein configuring the PWM circuit to form the first signal that is representative of the peak value of the primary current includes configuring a timing detection circuit to form a timing signal that is representative of a time interval that the secondary current is flowing in the secondary winding.

17. The method of claim 14 wherein configuring the PWM circuit to form the first signal that is representative of the peak value of the primary current includes configuring a current estimator circuit to receive the first signal and integrate the first signal over the time interval.

18. The method of claim 14 wherein configuring the PWM circuit to form the first signal that is representative of the peak value of the primary current includes configuring a current estimator circuit to charge a capacitor with the first signal over the time interval and to discharge the capacitor for another portion of a period of the power switch.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2017
From: CHEN, LEI; HSIEH, CHIH-HSIEN; TANG, YUE-HONG
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 041768/0669 →
Continuity (2)
Provisional Application 62324520 · Apr 19, 2016
Related Publication 20170302184A1 · Oct 19, 2017