Thin film transistor substrate and manufacturing method thereof
A thin film transistor array panel includes a first substrate, a gate line disposed on the first substrate and includes a lower layer including titanium, a middle layer including a transparent conductive material, and an upper layer including copper, a pixel electrode disposed on the first substrate and includes a lower layer including titanium, and an upper layer including the transparent conductive material, a gate insulating layer disposed on the gate line and the pixel electrode, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode, and a common electrode disposed on the passivation layer.
1. A liquid crystal display comprising:
a first substrate;
a gate line which is disposed on the first substrate and includes:
a lower layer including titanium;
a middle layer including a transparent conductive material; and
an upper layer including copper,
a common electrode which is disposed on the first substrate and consists of a lower layer and an upper layer:
the lower layer including titanium; and
the upper layer including the transparent conductive material,
a gate insulating layer disposed on the gate line and the common electrode;
a semiconductor layer disposed on the gate insulating layer;
a data line and a drain electrode disposed on the semiconductor layer;
a passivation layer which covers the data line and the drain electrode, and a contact hole which is defined in the passivation layer and exposes a part of the drain electrode; and
a pixel electrode electrically connected to the drain electrode through the contact hole,
a second substrate facing the first substrate;
a color filter positioned on the second substrate; and
a light source positioned under the second substrate,
wherein the light source is disposed closer to the second substrate compared to the first substrate.
2. The thin film transistor array panel of claim 1 , wherein
the gate line and the common electrode are positioned in or directly on a same plane.
3. The thin film transistor array panel of claim 1 , wherein
the transparent conductive material of the gate line and the common electrode includes indium zinc oxide.
4. The thin film transistor array panel of claim 3 , wherein
a thickness of the lower layer of the gate line and the common electrode including titanium in a cross section is in a range of about 20 angstrom to about 200 angstrom.
5. The thin film transistor array panel of claim 4 , wherein
a thickness of the middle layer of the gate line and the upper layer of the common electrode including the indium zinc oxide in the cross section is in a range of about 400 angstrom to about 500 angstrom.