IP Library Granted Patent US 10,103,088
Granted Patent B1
US 10,103,088 · App. 15/473,251 · Granted Oct 16, 2018

Integrated antenna for direct chip attach connectivity module package structures

Inventors: Quan Qi (Beaverton, OR); Brian R. Butcher (Queen Creek, AZ); Carlton E. Hanna (Santa Clara, CA); Hong Wei Hu (Gilbert, AZ)
Assignee: Intel IP Corporation
H01L23/4334H01L23/49816H01L23/5389H01L24/19H01L24/20H01L25/0652H01L2924/18165
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Quick Facts
Patent No.
US 10,103,088
App. No.
15/473,251
Granted
Oct 16, 2018
Kind
B1
Abstract

Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include a die disposed on a first substrate, at least one component adjacent the die on the first substrate, a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding material, a second substrate, wherein the first substrate is disposed on a top surface of the second substrate, and at least one communication structure disposed on a surface of the second substrate.

Claims (42)

1. A microelectronic package structure comprising:

a die on a first substrate;

at least one component adjacent the die on the first substrate;

a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding material;

a second substrate, wherein the first substrate is on a top surface of the second substrate, and wherein the second substrate comprises low density routing printed circuit board (PCB); and

at least one communication structure on a surface of the second substrate.

2. The microelectronic package structure of claim 1 wherein a top surface of the second substrate does not comprise the molding material.

3. The microelectronic package structure of claim 1 wherein a shielding material is on a top surface and on a side surface of the molding material.

4. The microelectronic package structure of claim 1 wherein an individual one of the at least one communication structure is on a top surface of the second substrate.

5. The microelectronic package structure of claim 1 wherein a first communication structure is on a bottom surface of the second substrate.

6. The microelectronic package structure of claim 5 wherein a second communication structure is on a top surface of the second substrate.

7. The microelectronic package structure of claim 1 wherein the at least one component and the at least one die are fully embedded in the molding material.

8. A microelectronic package structure comprising:

a die on a first substrate;

at least one component adjacent the die on the first substrate;

a molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material; and

a first portion of a first communication structure on a portion of a top surface of the molding material, and a second portion of the first communication structure through a portion of the molding material and on a top surface of the first substrate.

9. The microelectronic package structure of claim 8 wherein the first communication structure comprises an antenna structure, and wherein a shielding material is adjacent the antenna structure and is directly on a top surface of the molding material.

10. The microelectronic package structure of claim 8 wherein a second substrate is on a bottom surface of the first substrate.

11. The microelectronic package structure of claim 10 wherein a second communication structure is on a top surface of the second substrate.

12. The microelectronic package structure of claim 10 wherein a second communication structure is on a bottom surface of the second substrate.

13. The microelectronic package structure of claim 10 wherein a top surface of the second substrate comprises a second communication structure thereon, and a bottom surface of the second substrate comprises a third communication structure thereon.

14. The microelectronic package structure of claim 8 wherein a top surface and a side surface of the molding material comprises an RF shielding material thereon.

15. The microelectronic package structure of claim 8 , wherein a bottom surface of the first substrate comprises a second communication structure thereon.

16. A system comprising:

a processor to process data;

a memory for storage of data;

a transmitter or a receiver for transmission and reception of data;

and

a module including:

a die on a first substrate;

at least one component adjacent the die on the first substrate;

a molding material on the die and the at least one component, wherein the die and the at least one component are completely embedded in the molding component;

a second substrate, wherein the first substrate is on a top surface of the second substrate; and

a first antenna on a top surface of the second substrate, and a second antenna on a bottom surface of the second substrate.

17. The system of claim 16 wherein a top surface of the second substrate does not comprise the molding material thereon.

18. The method of claim 16 wherein the second substrate comprises a low density substrate.

19. The system of claim 16 further comprising wherein an RF shielding material is on a top surface of the molding material adjacent a communication structure on the molding material.

20. The system of claim 16 further comprising wherein the first substrate comprises an embedded trace substrate.

21. The system of claim 16 wherein a first portion of a first communication structure is on a portion of a top surface of the molding material, and a second portion of the first communication structure is through a portion of the molding material and is on a top surface of the first substrate.

22. The system of claim 21 wherein the first antenna is not below a footprint of the first substrate.

23. The system of claim 16 wherein the die comprises a wireless die or a system on a chip.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056337/0609 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2017
From: QI, QUAN; BUTCHER, BRIAN R.; HANNA, CARLTON E.; HU, HONG WEI
To: INTEL IP CORPORATION
Reel/Frame 042007/0495 →
Cited By (1)
US 12,347,782