DC-DC converter with gate charge re-use
A DC-DC converter includes an output power stage and a driver circuit. The output stage switches an input voltage to a switch node using a first transistor in response to a top-gate signal received at a top-gate node, and the switch node to ground using a second transistor in response to a bottom-gate signal received at a bottom-gate node. The driver circuit that provides the top- and bottom-gate signals in response to high- and low-side switch signals, respectively, activates the top-gate signal by actively regulating the top-gate node to a first voltage between a threshold voltage and a breakdown voltage of the first transistor using charge from the bottom-gate node, and activates the bottom-gate signal by actively regulating a second voltage provided to the bottom-gate node between a threshold voltage and a breakdown voltage of the second transistor using charge from the top-gate node.
1. A DC-DC converter comprising:
a dead-time control circuit having an input for receiving a pulse width modulation signal, a first output for providing a high-side switch signal, and a second output for providing a low side switch signal;
an output power stage for receiving an input voltage and switching said input voltage to a switch node using a first transistor in response to a top-gate signal received at a top-gate node, and for switching said switch node to ground using a second transistor in response to a bottom-gate signal received at a bottom-gate node; and
a driver circuit for providing said top-gate signal and said bottom-gate signal in response to said high-side switch signal and said low side switch signal, respectively, said driver circuit activating said top-gate signal using a first regulator that actively regulates said top-gate node to a first voltage between a threshold voltage and a breakdown voltage of said first transistor using charge from said bottom-gate node, and activating said bottom-gate signal using a second regulator that actively regulates a second voltage provided to said bottom-gate node between a threshold voltage and a breakdown voltage of said second transistor using charge from said top-gate node.
2. The DC-DC converter of claim 1 wherein:
said first transistor has a first current electrode for receiving said input voltage, a control electrode for receiving said top-gate signal, and a second current electrode coupled to said switch node; and
said second transistor has a first current electrode coupled to said switch node, a control electrode for receiving said bottom-gate signal, and a second current electrode coupled to ground.
3. The DC-DC converter of claim 2 wherein said first and second transistors comprise laterally diffused metal-oxide-semiconductor (LDMOS) transistors.
4. The DC-DC converter of claim 1 wherein said driver circuit comprises:
a high-side driver coupled between a voltage input terminal and an intermediate node for providing said top-gate signal in response to said high-side switch signal;
a tank capacitor having a first terminal coupled to said intermediate node, and a second terminal coupled to ground; and
a low side driver coupled between said intermediate node and ground for providing said bottom-gate signal in response to said low side switch signal.
5. The DC-DC converter of claim 4 wherein said high-side driver comprises:
a first driver having an input for receiving said high-side switch signal, an output, a positive power supply terminal for receiving said input voltage, and a negative power supply terminal;
a third transistor having a first current electrode coupled to said negative power supply terminal of said first driver, a control electrode, and a second current electrode coupled to said intermediate node; and
a first voltage source having a positive terminal for receiving said input voltage, and a negative terminal coupled to said control electrode of said third transistor.
6. The DC-DC converter of claim 5 , wherein said first voltage source provides a voltage between said first and second terminals thereof equal to a predetermined voltage plus a threshold voltage of said third transistor.
7. The DC-DC converter of claim 5 wherein said low side driver comprises:
a fourth transistor having a first current electrode coupled to said intermediate node, a control electrode, and a second current electrode;
a second driver having an input for receiving said low side switch signal, an output, a positive power supply terminal coupled to said second current electrode of said fourth transistor, and a negative power supply terminal coupled to ground; and
a second voltage source having a positive terminal coupled to said control electrode of said fourth transistor, and a negative terminal coupled to ground.
8. The DC-DC converter of claim 7 , wherein said second voltage source provides a voltage between said first and second terminals thereof equal to a predetermined voltage plus a threshold voltage of said fourth transistor.
9. The DC-DC converter of claim 1 wherein said driver circuit comprises:
a high-side driver coupled between a voltage input terminal and a first intermediate node for providing said top-gate signal in response to said high-side switch signal; and
a low side driver coupled between a second intermediate node and ground for providing said bottom-gate signal in response to said low side switch signal.
10. The DC-DC converter of claim 9 wherein said high-side driver comprises:
a first amplifier having a non-inverting input, an inverting input, an output coupled to said inverting input and to said first intermediate node, and a negative power supply input coupled to said second intermediate node;
a first voltage source having a positive terminal for receiving said input voltage, and a negative terminal coupled to said non-inverting input of said first amplifier;
a first capacitor having a first terminal for receiving said input voltage, and a second terminal coupled to said output of said first amplifier; and
a first driver coupled between a voltage input terminal and said first intermediate node for providing said top-gate signal in response to said high-side switch signal.
11. The DC-DC converter of claim 10 wherein said low side driver comprises:
a second amplifier having a non-inverting input, an inverting input, an output coupled to said inverting input and to said second intermediate node, and a positive power supply input coupled to said first intermediate node;
a second voltage source having a positive terminal for receiving said input voltage, and a negative terminal coupled to said non-inverting input of said second amplifier;
a second capacitor having a first terminal coupled to said output of said second amplifier, and a second terminal coupled to ground; and
a second driver coupled between said second intermediate node and ground for providing said bottom-gate signal in response to said low side switch signal.
12. The DC-DC converter of claim 1 wherein said driver circuit comprises:
a high-side driver coupled between a voltage input terminal and an intermediate node for providing said top-gate signal in response to said high-side switch signal;
a low side driver coupled between said intermediate node and ground for providing said bottom-gate signal in response to said low side switch signal; and
a bias capacitor having a first terminal coupled to said intermediate node, and a second terminal coupled to ground.
13. The DC-DC converter of claim 12 wherein said high-side driver comprises:
a first amplifier having a non-inverting input, an inverting input, an output coupled to said inverting input, and a negative power supply input coupled to said intermediate node;
a first voltage source having a positive terminal for receiving said input voltage, and a negative terminal coupled to said non-inverting input of said first amplifier;
a first capacitor having a first terminal for receiving said input voltage, and a second terminal coupled to said output of said first amplifier; and
a first driver coupled between a voltage input terminal and said output of said first amplifier for providing said top-gate signal in response to said high-side switch signal.
14. The DC-DC converter of claim 13 wherein said low side driver comprises:
a second amplifier having a non-inverting input, an inverting input, an output coupled to said inverting input, and a positive power supply input coupled to said intermediate node;
a second voltage source having a positive terminal for receiving said input voltage, and a negative terminal coupled to said non-inverting input of said second amplifier;
a second capacitor having a first terminal coupled to said output of said second amplifier, and a second terminal coupled to ground; and
a second driver coupled between said output of said second amplifier and ground for providing said bottom-gate signal in response to said low side switch signal.
15. A DC-DC power conversion system comprising:
an error amplifier having a first input for receiving a feedback signal, a second input for receiving a reference voltage, and an output;
an oscillator having an output for providing a clock signal; and
a pulse width modulator having a control input coupled to said output of said error amplifier, a clock input for receiving said clock signal, and an output for providing a pulse width modulator signal;
a dead-time control circuit having an input for receiving a pulse width modulation signal, a first output for providing a high-side switch signal, and a second output for providing a low side switch signal;
an output power stage for receiving an input voltage and switching said input voltage to a switch node using a first transistor in response to a top-gate signal received at a top-gate node, and for switching said switch node to ground using a second transistor in response to a bottom-gate signal received at a bottom-gate node; and
a driver circuit for providing said top-gate signal and said bottom-gate signal in response to said high-side switch signal and said low side switch signal, respectively, said driver circuit activating said top-gate signal using a first regulator that actively regulates said top-gate node to a first voltage between a threshold voltage and a breakdown voltage of said first transistor using charge from said bottom-gate node, and activating said bottom-gate signal using a second regulator that actively regulates a second voltage provided to said bottom-gate node between a threshold voltage and a breakdown voltage of said second transistor using charge from said top-gate node.
16. The DC-DC power conversion system of claim 15 , wherein said error amplifier, said oscillator, said pulse width modulator, said dead-time control circuit, said driver circuit, and said output power stage are combined in a single monolithic integrated circuit.
17. The DC-DC power conversion system of claim 15 , further comprising:
an inductor having a first terminal coupled to said switch node, and a second terminal for providing an output voltage; and
a capacitor having a first terminal coupled to said second terminal of said inductor, and a second terminal coupled to ground.
18. The DC-DC power conversion system of claim 15 wherein:
said first transistor has a first current electrode for receiving said input voltage, a control electrode for receiving said top-gate signal, and a second current electrode coupled to said switch node; and
said second transistor has a first current electrode coupled to said switch node, a control electrode for receiving said bottom-gate signal, and a second current electrode coupled to ground.
19. The DC-DC power conversion system of claim 18 wherein said first and second transistors comprise laterally diffused metal-oxide-semiconductor (LDMOS) transistors.
20. A method comprising:
receiving a pulse width modulation signal;
providing a high-side switch signal and a low side switch signal with a dead time therebetween in response to said pulse width modulation signal;
driving a top-gate node coupled to a gate of a first transistor in response to said high-side switch signal using a first regulator that actively regulates said top-gate node to a first voltage between a threshold voltage and a breakdown voltage of said first transistor using charge from a bottom-gate node coupled to a gate of a second transistor; and
driving said bottom-gate node in response to said low side switch signal using a second regulator that actively regulates said bottom-gate node to a second voltage between a threshold voltage and a breakdown voltage of said second transistor using charge from said top-gate node.
21. The method of claim 20 further comprising:
switching an input voltage to a switch node using said first transistor in response to said driving said top-gate node; and
switching said switch node to ground using said second transistor in response to said driving said bottom-gate node.
22. The method of claim 20 further comprising:
forming a tank voltage using a tank capacitor;
clamping a top-gate voltage on said top-gate node to said first voltage using said tank voltage; and
clamping a bottom-gate voltage on said bottom-gate node to said second voltage using said tank voltage.
23. The method of claim 20 wherein:
driving said top-gate node comprises driving a gate of a first LDMOS transistor; and
driving said bottom-gate node comprises driving a gate of a second LDMOS transistor.