IP Library Granted Patent US 10,469,775
Granted Patent B2
US 10,469,775 · App. 15/476,060 · Granted Nov 5, 2019

High dynamic range storage gate pixel circuitry

Inventors: John P. McCarten (Penfield, NY); Hung Q. Doan (Rochester, NY); Robert Kaser (Spencerport, NY)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N5/35581H04N5/3532H04N5/3592H04N5/37452
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Quick Facts
Patent No.
US 10,469,775
App. No.
15/476,060
Granted
Nov 5, 2019
Kind
B2
Abstract

Image sensors may include image sensor pixels that support high dynamic range (HDR) global shutter function. An image sensor pixel may include a photodiode that is coupled to multiple storage gate nodes via respective charge transfer gates. Each of the multiple storage gate nodes may be configured to store charge corresponding to different exposure periods. The storage gate nodes may be coupled in parallel or in series with the photodiode. Charge from the different exposure times can then be merged to produce a high dynamic range image signal.

Claims (50)

1. An image sensor comprising:

an image sensor pixel that comprises: a photodiode;

a first storage gate node that stores charge integrated at the photodiode for a first exposure period;

a second storage gate node that stores charge integrated at the photodiode for a second exposure period that is different than the first exposure period, wherein the photodiode is electrically connected to the first and second storage gate nodes via respective first and second parallel paths;

a first floating diffusion region interposed between the first storage gate node and a first column line; and

a second floating diffusion region interposed between the second storage gate node and a second column line; and

an additional image sensor pixel that comprises:

an additional photodiode; and

a third storage gate node coupled to the additional photodiode, wherein the first floating diffusion region is interposed between the third storage gate node and the first column line.

2. The image sensor of claim 1 , wherein the charge collected during the first exposure period and the charge collected during the second exposure period are linearly related.

3. The image sensor of claim 2 , wherein the first exposure period is at least two times longer than the second exposure period.

4. The image sensor of claim 2 , wherein the first exposure period is at least four times longer than the second exposure period.

5. The image sensor of claim 2 , wherein the first exposure period is at least ten times longer than the second exposure period.

6. The image sensor of claim 1 , the image sensor pixel further comprising:

a first transfer gate coupled between the photodiode and the first storage gate node; and

a second transfer gate coupled between the photodiode and the second storage gate node.

7. The image sensor of claim 1 , wherein the charge stored in the first and second storage nodes is read out in a rolling shutter fashion.

8. The image sensor of claim 1 , further comprising:

control circuitry configured to control the image sensor pixel:

to integrate the charge for the first exposure time by accumulating the charge during a plurality of partial exposure times summing up to the first exposure time; and

to integrate the charge for the second exposure time, wherein at least part of the second exposure time occurs between first and second given partial exposure times in the plurality of partial exposure times.

9. The image sensor of claim 1 , wherein the first floating diffusion region is coupled to a first source follower transistor and the second floating diffusion region is coupled to a second source follower transistor.

10. A method for operating an image sensor, the method comprising:

receiving light at a photodiode;

with the photodiode, accumulating charge for a first exposure time by accumulating the charge during a plurality of partial exposure times summing up to the first exposure time;

transferring the charge accumulated for the first exposure time to a first storage gate node;

with the photodiode, accumulating charge for a second exposure time, wherein at least part of the second exposure time occurs between first and second given partial exposure times in the plurality of partial exposure times; and

transferring the charge accumulated for the second exposure time to a second storage gate node that is different than the first storage gate node.

11. The method of claim 10 , wherein the first exposure time is at least ten times longer than the second exposure time.

12. The method of claim 10 , further comprising:

with the photodiode, accumulating charge for a third exposure time, wherein the first, second, and third exposure times are independently controlled and are different in duration; and

transferring the charge accumulated for the third exposure time to a third storage gate node that is different than the first and second storage gate nodes.

13. The method of claim 10 , further comprising:

transferring charge between the first and second storage gate nodes.

14. The method of claim 10 , wherein the first and second exposure times are independently controlled.

15. The method of claim 10 , further comprising:

generating an image based on the charge accumulated for the first exposure time and the charge accumulated for the second exposure time.

16. An electronic device comprising:

a camera module having an image sensor, the image sensor comprising an image sensor pixel, and the image sensor pixel comprising:

a photodiode;

a first storage gate region that is coupled to the photodiode and that stores charge for a first exposure time;

a second storage gate region that is coupled to the photodiode and that stores charge for a second exposure time;

a floating diffusion region, wherein the first storage gate region is interposed between the second storage gate region and the floating diffusion region;

a first charge transfer transistor that directly connects the photodiode to the first storage gate region; and

a second charge transfer transistor that directly connects the photodiode to the second storage gate region.

17. The electronic device of claim 16 , the image sensor pixel further comprising:

a barrier implant region interposed between the first and second storage gate regions, wherein the barrier implant region has a terminal that receives a control signal.

18. The electronic device of claim 17 , the image sensor pixel further comprising:

a lateral overflow drain region that physically contacts the barrier implant region, the first storage gate region, and second storage gate region.

19. The electronic device of claim 16 , wherein the first and second storage gate regions are coupled in series to the floating diffusion region, the first storage gate region is connected to the photodiode via a first path, and the second storage gate region is connected to the photodiode via a second path that is separate from the first path.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2017
From: MCCARTEN, JOHN P.; DOAN, HUNG Q.; KASER, ROBERT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 041812/0805 →
Continuity (1)
Related Publication 20180288343A1 · Oct 4, 2018
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