Device blanking
A method and apparatus is disclosed for protecting electronic devices from security breaches (e.g., in the form of DPA attacks) by managing input/output (I/O) pin states. The technique is particularly useful in financial applications in which data security related operations, such as those involving cryptography, are performed by payment card readers, and the power supplied to drive the operations are measured and analyzed by attackers to extract sensitive information. The technique prevents any external device from measuring the operation power by disabling the I/O pins. The I/O pins are set to a logic low at any given time a data security related operation is performed. As a result, no communication with the external environment is possible during the data security operation, and external power measurements by DPAs are prevented.
1. An apparatus comprising:
at least one input/output terminal;
an input/output controller coupled to the at least one input/output terminal to connect the at least one input/output terminal to a logic low in a first state and permit input/output operations at the at least one input/output terminal in a second state; and
a processor coupled to the input/output controller, the processor configured to identify an occurrence of a data processing operation to protect, cause the input/output controller to enter the first state based on the occurrence of the data processing operation, cause the input/output controller to enter the second state based on the completion of the data processing operation, and to communicate via the at least one input/output terminal during the second state.
2. The apparatus of claim 1 , wherein the data processing operation comprises a data security operation.
3. The apparatus of claim 2 , wherein the data security operation comprises a cryptographic operation.
4. The apparatus of claim 3 , wherein the cryptographic operation comprises at least one of:
generation of a cryptographic hash;
verification of a cryptographic hash; or
encryption of a cryptographic hash.
5. The apparatus of claim 1 , wherein the connection of the at least one input/output terminal to a logic low comprises a connection of the at least one input/output terminal to ground.
6. The apparatus of claim 1 , wherein the at least one input/output terminal comprises a plurality of input/output terminals, and wherein the input/output controller is coupled to each of the plurality of input/output terminals to connect each of the plurality of input/output terminals to the logic low in the first state and to permit input/output operations at each of the plurality of input/output terminals in the second state.
7. The apparatus of claim 1 , wherein the input/output controller and the processor are located within an internal environment of the apparatus, and wherein at least a portion of the at least one input/output terminal is located at an external environment of the apparatus.
8. An apparatus comprising:
at least one input/output terminal;
an input/output controller coupled to the at least one input/output terminal to disable input functionality for the at least one input/output terminal in a first state and to enable input functionality for the at least one input/output terminal in a second state; and
a processor coupled to the input/output controller, the processor configured to identify an occurrence of a data processing operation to protect, cause the input/output controller to enter the first state in response to the occurrence of the data processing operation, cause the input/output controller to enter the second state in response to the completion of the data processing operation, and to communicate via the plurality of input/output terminals during the second state.
9. The apparatus of claim 8 , wherein the data processing operation comprises a cryptographic operation.
10. The apparatus of claim 9 , wherein the cryptographic operation comprises at least one of:
generation of a cryptographic hash;
verification of a cryptographic hash; or
encryption of a cryptographic hash.
11. The apparatus of claim 8 , wherein the input/output controller and the processor are located within an internal environment of the apparatus, and wherein at least a portion of the at least one input/output terminal is located at an external environment of the apparatus.
12. The apparatus of claim 8 , wherein the input functionality is disabled by setting the at least one input/output terminal to a logic low.
13. The apparatus of claim 8 , wherein the input functionality is disabled by setting the at least one input/output terminal to ground.
14. The apparatus of claim 8 , wherein the input functionality is disabled by setting the at least one input/output terminal to an output state.
15. The apparatus of claim 8 , wherein the at least one input/output terminal comprises a plurality of input/output terminals, and wherein the input/output controller is coupled to disable input functionality at each of the plurality of input/output terminals in the first state and enable input functionality at each of the plurality of input/output terminals in the second state.
16. A method comprising:
identifying an occurrence of a data processing operation to protect;
causing an input/output controller to enter a first state based on the occurrence of the data processing operation;
connecting at least one input/output terminal to a logic low in the first state;
causing the input/output controller to enter a second state based on the completion of the data processing operation;
permitting input/output operations at the at least one input/output terminal in the second state; and
communicating via the at least one input/output terminal during the second state.
17. The method of claim 16 , wherein the data processing operation comprises a data security operation.
18. The method of claim 17 , wherein the data security operation comprises a cryptographic operation.
19. The method of claim 18 , wherein the cryptographic operation comprises at least one of:
generating a cryptographic hash;
verifying a cryptographic hash; or
encrypting a cryptographic hash.
20. The method of claim 16 , wherein connecting the at least one input/output terminal to a logic low comprises connecting the at least one input/output terminal to ground.
21. The method of claim 16 , wherein the at least one input/output terminal comprises a plurality of input/output terminals, wherein connecting the at least one input/output terminal to a logic low in the first state comprises connecting each of the plurality of input/output terminals to the logic low in the first state, and wherein permitting input/output operations at the at least one input/output terminal in the second state comprises permitting input/output operations at each of the plurality of input/output terminals in the second state.
22. The method of claim 16 , wherein the input/output controller and the processor are located within an internal environment of an apparatus, and wherein at least a portion of the at least one input/output terminal is located at an external environment of the apparatus.
23. A method comprising:
identifying an occurrence of a data processing operation to protect;
causing an input/output controller to enter a first state based on the occurrence of the data processing operation;
disabling input functionality of at least one input/output terminal in the first state;
causing the input/output controller to enter a second state based on the completion of the data processing operation;
enabling input functionality of the at least one input/output terminal in the second state; and
communicating via the at least one input/output terminal during the second state.
24. The method of claim 23 , wherein the data processing operation comprises a cryptographic operation.
25. The method of claim 24 , wherein the cryptographic operation comprises at least one of:
generating a cryptographic hash;
verifying a cryptographic hash; or
encrypting a cryptographic hash.
26. The method of claim 23 , wherein disabling the at least one input/output terminal comprises connecting the at least one input/output terminal to a logic low.
27. The method of claim 23 , wherein disabling the at least one input/output terminal comprises connecting the at least one input/output terminal to ground.
28. The method of claim 23 , wherein disabling the at least one input/output terminal comprises connecting the at least one input/output terminal to an output state.
29. The method of claim 23 , wherein the at least one input/output terminal comprises a plurality of input/output terminals, wherein disabling input functionality of the at least one input/output terminal comprises disabling input functionality of each of the plurality of input/output terminals in the first state, and wherein enabling input functionality of the at least one input/output terminal comprises enabling input functionality of each of the plurality of input/output terminals in the second state.
30. The method of claim 23 , wherein the input/output controller and the processor are located within an internal environment of an apparatus, and wherein at least a portion of the at least one input/output terminal is located at an external environment of the apparatus.