IP Library Granted Patent US 10,424,107
Granted Patent B2
US 10,424,107 · App. 15/477,049 · Granted Sep 24, 2019

Hierarchical depth buffer back annotaton

Inventors: Vasanth Ranganathan (El Dorado Hills, CA); Saikat Mandal (Folsom, CA); Saurabh Sharma (El Dorado Hills, CA); Vamsee Vardhan Chivukula (Folsom, CA); Karol A. Szerszen (Rancho Cordova, CA); Aleksander Olek Neyman (Gdansk, PL); Altug Koker (El Dorado Hills, CA); Prasoonkumar Surti (Folsom, CA); Abhishek Appu (El Dorado Hills, CA); Joydeep Ray (Folsom, CA); Art Hunter (Folsom, CA); Luis F. Cruz Camacho (Folsom, CA); Akshay R. Chada (Folsom, CA)
Assignee: Intel Corporation
G06T15/405G06T15/005
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Quick Facts
Patent No.
US 10,424,107
App. No.
15/477,049
Granted
Sep 24, 2019
Kind
B2
Abstract

Briefly, in accordance with one or more embodiments, a processor performs a coarse depth test on pixel data, and performs a final depth test on the pixel data. Coarse depth data is stored in a coarse depth cache, and per pixel depth data is stored in a per pixel depth cache. If a result of the coarse depth test is ambiguous, the processor is to read the per pixel depth data from the per pixel depth cache, and to update the coarse depth data with the per pixel depth data if the per pixel depth data has a smaller depth range than the coarse depth data.

Claims (42)

1. An apparatus, comprising:

a processor to perform a coarse depth test, to perform an intermediate depth test, and to perform a final depth test; and

a memory to store coarse depth data in a coarse depth cache, to store intermediate depth data in a back-annotation cache, and to store per pixel depth data in a per pixel depth cache;

wherein if a result of the coarse depth test is ambiguous, the processor is to:

read the per pixel depth data from the per pixel depth cache,

perform the intermediate depth test on the per pixel depth data to provide the intermediate depth data to the back-annotation cache, and

update the coarse depth data with the intermediate depth data if the intermediate depth data has a smaller depth range than the coarse depth data, wherein the processor is to perform the coarse depth test on the updated coarse depth data.

2. The apparatus of claim 1 , wherein the coarse depth test and the intermediate depth test are performed before pixel shading is performed, and the final depth test is performed after pixel shading is performed.

3. The apparatus of claim 1 , wherein the per pixel depth data is read from the per pixel depth cache when the intermediate depth test is performed.

4. The apparatus of claim 1 , wherein the processor is to read the per pixel depth data after depth shading is performed on the pixel data and after the final depth test is performed.

5. The apparatus of claim 1 , wherein the processor is to perform the intermediate depth test on the per pixel depth data after reading the per pixel depth data by finding a minimum depth value and a maximum depth value in the per pixel depth data.

6. The apparatus of claim 1 , wherein the result of the coarse depth test is ambiguous if the result is neither pass nor fail.

7. The apparatus of claim 1 , wherein the processor is to set a flag to indicate if a minimum depth value needs to be updated, if a maximum depth value needs to be updated, or a combination thereof.

8. The apparatus of claim 1 , wherein the processor is to comprise one or more of: a Graphics Processing Unit (GPU) or a processor core, or a combination thereof.

9. A method comprising:

performing a coarse depth test on pixel data and storing coarse depth data in a coarse depth cache;

performing a final depth test on the pixel data, and storing per pixel depth data in a per pixel depth cache; and

determining if a result of the coarse depth test is ambiguous, and if the result is ambiguous:

reading the per pixel depth data from the per pixel depth cache;

performing an intermediate depth test on the per pixel depth data to provide intermediate depth data to a back-annotation cache;

updating the coarse depth data with the intermediate depth data if the intermediate depth data has a smaller depth range than the coarse depth data; and

performing the coarse depth test on the updated coarse depth data.

10. The method of claim 9 , wherein said performing the coarse depth test and the intermediate depth test occur before pixel shading, and said performing the final depth test occurs after pixel shading.

11. The method of claim 9 , wherein said reading the per pixel depth data from the per pixel depth cache occurs when the intermediate depth test occurs.

12. The method of claim 9 , wherein said reading the per pixel depth data from the per pixel depth cache occurs after depth shading is performed on the pixel data and after performing the final depth test.

13. The method of claim 9 , further comprising performing the intermediate depth test on the per pixel depth data that is read from the per pixel depth cache by finding a minimum depth value and a maximum depth value in the per pixel depth data.

14. The method of claim 9 , wherein the result of the coarse depth test is ambiguous of the result is neither pass nor fail.

15. The method of claim 9 , further comprising setting a flag to indicate if a minimum depth value needs to be updated, if a maximum depth value needs to be updated, or a combination thereof.

16. One or more non-transitory computer-readable media comprising one or more instructions that if executed on at least one processor configure the at least one processor to perform one or more operations to:

perform a coarse depth test on the pixel data and store coarse depth data in a coarse depth cache;

perform a final depth test on the pixel data, and store per pixel depth data in a per pixel depth cache; and

determine if a result of the coarse depth cache is ambiguous, and if the result is ambiguous:

read the per pixel depth data from the per pixel depth cache;

perform an intermediate depth test on the per pixel depth data to provide intermediate depth data to a back-annotation cache;

update the coarse depth data with the intermediate depth data if the intermediate depth data has a smaller depth range than the coarse depth data; and

perform the coarse depth test on the updated coarse depth data.

17. The one or more non-transitory computer-readable media of claim 16 , wherein the coarse depth test and the intermediate depth test occur before pixel shading, and the final depth test occurs after pixel shading.

18. The one or more non-transitory computer-readable media of claim 16 , wherein the per pixel depth data is read from the per pixel depth cache when the intermediate depth test occurs.

19. The one or more non-transitory computer-readable media of claim 16 , wherein the per pixel depth data from the per pixel depth cache after depth shading is performed on the pixel data and after the final depth test is performed.

20. The one or more non-transitory computer-readable media of claim 16 , wherein the instructions if executed further configure the at least one processor to perform operations to perform the intermediate depth test on the per pixel depth data that is read from the per pixel depth cache by finding a minimum depth value and a maximum depth value in the per pixel depth data.

21. The one or more non-transitory computer-readable media of claim 16 , wherein the result of the coarse depth test is ambiguous of the result is neither pass nor fail.

22. The one or more non-transitory computer-readable media of claim 16 , wherein the instructions if executed further configure the at least one processor to set a flag to indicate if a minimum depth value needs to be updated, if a maximum depth value needs to be updated, or a combination thereof.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2021
From: RAY, JOYDEEP
To: INTEL CORPORATION
Reel/Frame 056448/0492 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2019
From: HUNTER, ART; CRUZ CAMACHO, LUIS F.; CHADA, AKSHAY R.
To: INTEL CORPORATION
Reel/Frame 048431/0363 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2018
From: RANGANATHAN, VASANTH; MANDAL, SAIKAT; SHARMA, SAURABH; CHIVUKULA, VAMSEE VARDHAN; SZERSZEN, KAROL A.; NEYMAN, ALEKSANDER OLEK; KOKER, ALTUG; APPU, ABHISHEK; SURTI, PRASOONKUMAR
To: INTEL CORPORATION
Reel/Frame 045245/0496 →
Continuity (1)
Related Publication 20180286113A1 · Oct 4, 2018