Sector cache for compression
In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.
1. A general-purpose graphics processing device comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to execute the stream of instructions;
a general-purpose graphics processing compute block comprising a plurality of execution units;
a shared cache memory communicatively coupled to the plurality of execution units;
a memory interface communicatively coupled to the shared cache memory comprising a processor to:
structure the cache memory is structured into a plurality of sectors, each sector in the plurality of sectors comprising at least a first cache line and a second cache line, wherein the first cache line and the second cache line in each of the plurality of sectors are indicated by a pairing bit field assigned by the processor that associates the first cache line and the second cache line with a sector in the plurality of sectors and which is included with cache access operations and in a cache tag field;
receive a cache access request to the shared cache memory, the cache access request comprising the paring bit field; and
use the pairing bit field to locate the at least a first cache line and a second cache line associated with the cache access request to the shared cache memory; and
a data compression unit communicatively coupled to the cache memory, wherein the data compression unit operates at a sector-level granularity.
2. The general-purpose graphics processing device of claim 1 , wherein the general-purpose graphics processing compute block includes multiple compute clusters, each compute cluster including multiple graphics multiprocessors.
3. The general-purpose graphics processing device of claim 2 , further comprising a processor to match the pairing bit included with a cache access operation to the pairing bit in a cache tag field.
4. The general-purpose graphics processing device of claim 1 , further comprising a processor to implement a victim selection algorithm during a cache eviction.
5. The general-purpose graphics processing device of claim 4 , wherein the victim selection algorithm assigns a high priority to cache sectors which are invalid.
6. The general-purpose graphics processing device of claim 4 , wherein the victim selection algorithm assigns a high priority to cache sectors which are valid and include at least one invalid cacheline.
7. The general-purpose graphics processing device of claim 4 , wherein the victim selection algorithm assigns a low priority to cache sectors which are valid and include at least all invalid cachelines.
8. The general-purpose graphics processing device of claim 1 wherein the general-purpose graphics processing device is an add-in card connected to the separate general-purpose processor via a system bus.
9. The general-purpose graphics processing device of claim 1 , wherein the plurality of execution units are on a single integrated circuit.
10. An electronic device, comprising:
a central processing unit; and
a general-purpose graphics processing device comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to execute the stream of instructions;
a general-purpose graphics processing compute block comprising a plurality of execution units;
a shared cache memory communicatively coupled to the plurality of execution units;
a memory interface communicatively coupled to the shared cache memory comprising a processor to:
structure the cache memory is structured into a plurality of sectors, each sector in the plurality of sectors comprising at least a first cache line and a second cache line, wherein the first cache line and the second cache line in each of the plurality of sectors are indicated by a pairing bit field assigned by the processor that associates the first cache line and the second cache line with a sector in the plurality of sectors and which is included with cache access operations and in a cache tag field;
receive a cache access request to the shared cache memory, the cache access request comprising the paring bit field; and
use the pairing bit field to locate the at least a first cache line and a second cache line associated with the cache access request to the shared cache memory; and
a data compression unit communicatively coupled to the cache memory, wherein the data compression unit operates at a sector-level granularity.
11. The electronic device of claim 10 , wherein the general-purpose graphics processing compute block includes multiple compute clusters, each compute cluster including multiple graphics multiprocessors.
12. The electronic device of claim 11 , further comprising a processor to match the pairing bit included with a cache access operation to the pairing bit in a cache tag field.
13. The electronic device of claim 10 , further comprising a processor to implement a victim selection algorithm during a cache eviction.
14. The electronic device of claim 13 , wherein the victim selection algorithm assigns a high priority to cache sectors which are invalid.
15. The electronic device of claim 13 , wherein the victim selection algorithm assigns a high priority to cache sectors which are valid and include at least one invalid cache line.
16. The electronic device of claim 13 , wherein the victim selection algorithm assigns a low priority to cache sectors which are valid and include at least all invalid cache lines.
17. The electronic device of claim 10 , wherein the general-purpose graphics processing device is an add-in card connected to the separate general-purpose processor via a system bus.
18. The electronic device of claim 10 , wherein the plurality of execution units are on a single integrated circuit.