Successive-approximation register (SAR) analog-to-digital converter (ADC) with ultra low burst error rate
View Patent ↗Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.
1. A method, comprising:
applying analog-to-digital conversion to an analog input via a plurality of successive conversion cycles;
assessing a meta-stability state corresponding to said analog-to-digital conversion, based on results of all of said plurality of successive conversion cycles, said assessing comprising:
determining, for each conversion cycle, that meta-stability occurred based on a change in an outcome of a matching search performed for that conversion cycle; and
wherein said change occurs after triggering of a next conversion cycle; and
controlling generating a digital output corresponding to said analog input based on said assessing of said meta-stability state.
2. The method of claim 1 , wherein each conversion cycle corresponds to a particular bit in said digital output.
3. The method of claim 1 , comprising triggering a next one of said plurality of successive conversion cycles based on a cycle termination event associated with a current one of said plurality of successive conversion cycles.
4. The method of claim 3 , wherein said cycle termination event comprises expiry of a corresponding fixed delay.
5. The method of claim 1 , wherein said controlling of generating of said digital output comprises adjusting at least a portion of said digital output based on detection of a meta-stability event.
6. The method of claim 1 , comprising detecting meta-stability for each one of said plurality of successive conversion cycles.
7. The method of claim 6 , comprising determining that meta-stability occurred for each conversion cycle when said matching search fails to settle within a corresponding time period.
8. The method of claim 6 , comprising:
generating information relating to a result of said detecting of meta-stability during each conversion cycle until end of said analog-to-digital conversion; and
retaining said information until end of said analog-to-digital conversion.
9. The method of claim 8 , comprising assessing said meta-stability state based on said retained information.
10. The method of claim 1 , comprising assessing said meta-stability state after completing all of said plurality of successive conversion cycles.
11. A system, comprising:
one or more circuits for use in a signal processing component, said signal processing component being configurable to perform analog-to-digital conversions, wherein said one or more circuits are operable to:
apply analog-to-digital conversion to an analog input via a plurality of successive conversion cycles;
assess a meta-stability state corresponding to said analog-to-digital conversion, based on results of all of said plurality of successive conversion cycles, said assessing comprising:
determining, for each conversion cycle, that meta-stability occurred based on a change in an outcome of a matching search performed for that conversion cycle; and
wherein said change occurs after triggering of a next conversion cycle; and
control generating a digital output corresponding to said analog input based on said assessing of said meta-stability state.
12. The system of claim 11 , wherein each conversion cycle corresponds to a particular bit in said digital output.
13. The system of claim 11 , wherein said one or more circuits are operable to trigger a next one of said plurality of successive conversion cycles based on a cycle termination event associated with a current one of said plurality of successive conversion cycles.
14. The system of claim 13 , wherein said cycle termination event comprises expiry of a corresponding fixed delay.
15. The system of claim 11 , wherein said controlling of generating of said digital output comprises adjusting at least a portion of said digital output based on detection of a meta-stability event.
16. The system of claim 11 , wherein said one or more circuits are operable to detect meta-stability for each one of said plurality of successive conversion cycles.
17. The system of claim 16 , wherein said one or more circuits are operable to determine that meta-stability occurred for each conversion cycle when said matching search fails to settle within a corresponding time period.
18. The system of claim 16 , wherein said one or more circuits are operable to:
generate information relating to a result of said detecting of meta-stability during each conversion cycle until end of said analog-to-digital conversion; and
retain said information until end of said analog-to-digital conversion.
19. The system of claim 18 , wherein said one or more circuits are operable to assess said meta-stability state based on said retained information.
20. The system of claim 11 , wherein said one or more circuits are operable to assess said meta-stability state after completing all of said plurality of successive conversion cycles.