Solid state storage device and read control method thereof
View Patent ↗A solid state storage device includes a non-volatile memory and a controlling circuit. In a first read retry process, the controlling circuit judges whether an information corresponding to a first block of the non-volatile memory is recorded in the cache table. If the information is not recorded in the cache table, the controlling circuit sequentially provides plural predetermined retry read voltage sets to the non-volatile memory according to a sequence of the plural predetermined retry read voltage sets in the retry table and performs a read retry operation. If a read data of the first block is successfully decoded through the read retry operation according to a first predetermined retry read voltage set of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records the first predetermined retry read voltage set into the cache table.
1. A read control method for a solid state storage device, the solid state storage device comprising a non-volatile memory and a controlling circuit, the non-volatile memory comprising plural blocks, the controlling circuit being connected with the non-volatile memory and comprising a cache table and a retry table, plural predetermined retry read voltage sets being recorded in the retry table, the read control method comprising steps of:
implementing a first read retry process to perform a read retry operation on a first block of the plural blocks; and
judging whether at least one retry read voltage set corresponding to the first block is recorded in the cache table,
wherein if the at least one retry read voltage set corresponding to the first block is recorded in the cache table, the read retry operation is performed on the first block according to the at least one retry read voltage set, and
wherein if the at least one retry read voltage set corresponding to the first block is not recorded in the cache table, the read retry operation is performed on the first block according to the plural predetermined retry read voltage sets in the retry table,
wherein if a read data of the first block is not successfully decoded through the read retry operation according to the at least one retry read voltage set in the cache table, the controlling circuit performs the read retry operation on the first block according to the plural predetermined retry read voltage sets in the retry table.
2. The read control method as claimed in claim 1 , wherein if the at least one retry read voltage set corresponding to the first block is recorded in the cache table, a read data of the first block has been successfully decoded through the read retry operation according to the at least one retry read voltage set.
3. The read control method as claimed in claim 1 , wherein if a read data of the first block is successfully decoded through the read retry operation according to a first predetermined retry read voltage set of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records the first predetermined retry read voltage set into the cache table at a location corresponding to the first block.
4. The read control method as claimed in claim 1 , further comprising a step of judging whether a specified code corresponding to the first block is recorded in the cache table before the read retry operation is performed on the first block according to the cache table, wherein if the specified code corresponding to the first block is recorded in the cache table, the first read retry process is stopped, and the controlling circuit implements a second read retry process, wherein the first read retry process and the second read retry process use different decoding methods.
5. A solid state storage device, comprising:
a non-volatile memory comprising a first block; and
a controlling circuit connected with the non-volatile memory, wherein the controlling circuit comprises a cache table and a retry table, and plural predetermined retry read voltage sets are recorded in the retry table,
wherein in a first read retry process, the controlling circuit judges whether an information corresponding to the first block is recorded in the cache table, wherein if the information corresponding to the first block is not recorded in the cache table, the controlling circuit sequentially provides the plural predetermined retry read voltage sets to the non-volatile memory according to a sequence of the plural predetermined retry read voltage sets in the retry table and performs a read retry operation on the first block,
wherein if a read data of the first block is successfully decoded through the read retry operation according to a first predetermined retry read voltage set of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records the first predetermined retry read voltage set into the cache table.
6. The solid state storage device as claimed in claim 5 , wherein before the first read retry process, the controlling circuit provides a default read voltage set to the non-volatile memory to read the first block, wherein if the read data of the first block is not successfully decoded according to the default read voltage set, the controlling circuit performs the first read retry process.
7. The solid state storage device as claimed in claim 5 , wherein if the information corresponding to the first block is recorded in the cache table, the controlling circuit further judges whether the information contains a specified code, wherein if the information does not contain the specified code, the controlling circuit provides at least one retry read voltage set of the information to the non-volatile memory and performs the read retry operation on the first block according to the at least one retry read voltage set.
8. The solid state storage device as claimed in claim 7 , wherein if the read data of the first block is not successfully decoded through the read retry operation according to the at least one retry read voltage set in the cache table, the controlling circuit sequentially provides the plural predetermined retry read voltage sets to the non-volatile memory according to the sequence of the plural predetermined retry read voltage sets in the retry table and performs the read retry operation on the first block.
9. The solid state storage device as claimed in claim 5 , wherein if the read data of the first block is not successfully decoded through the read retry operation according to all of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records a specified code into the cache table.
10. A read control method for a solid state storage device, the solid state storage device comprising a non-volatile memory and a controlling circuit, the non-volatile memory comprising plural blocks, the controlling circuit being connected with the non-volatile memory and comprising a cache table and a retry table, plural predetermined retry read voltage sets being recorded in the retry table, the read control method comprising steps of:
implementing a first read retry process to perform a read retry operation on a first block of the plural blocks; and
judging whether an information corresponding to the first block is recorded in the cache table,
wherein if the information corresponding to the first block is not recorded in the cache table, the read retry operation is performed on the first block according to a sequence of the plural predetermined retry read voltage sets in the retry table, and
wherein if the at least one retry read voltage set corresponding to the first block is not recorded in the cache table, the read retry operation is performed on the first block according to the sequence of the plural predetermined retry read voltage sets in the retry table,
wherein if a read data of the first block is successfully decoded through the read retry operation according to a first predetermined retry read voltage set of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records the first predetermined retry read voltage set into the cache table.
11. The read control method as claimed in claim 10 , wherein if the information corresponding to the first block is recorded in the cache table, the read retry operation is performed on the first block according to at least one retry read voltage set of the information in the cache table.
12. The read control method as claimed in claim 11 , wherein if the read data of the first block is not successfully decoded through the read retry operation according to the at least one retry read voltage set in the cache table, the controlling circuit performs the read retry operation on the first block according to the plural predetermined retry read voltage sets in the retry table.
13. The read control method as claimed in claim 10 , wherein if the read data of the first block is not successfully decoded through the read retry operation according to all of the plural predetermined retry read voltage sets in the retry table, the controlling circuit records a specified code into the cache table.