Display device
View Patent ↗A display device is disclosed, which includes: a substrate having a display region and a peripheral region adjacent to the display region; a first transistor disposed on the display region and comprising a first channel layer, wherein the first channel layer includes an oxide semiconductor layer; and a second transistor disposed on the peripheral region and comprising a second channel layer, wherein the second channel layer includes a silicon semiconductor layer. Herein, a first ratio, which is a ratio of a first channel width of the first channel layer to the first channel length thereof, is greater than or equal to 0.4 and less than or equal to 4.5; and a second ratio, which is a ratio of a second channel width of the second channel layer to a second channel length thereof, is greater than or equal to 0.05 and less than or equal to 0.8.
1. A display device, comprising:
a first substrate having a display region and a peripheral region being adjacent to the display region;
a first transistor disposed on the display region and comprising a first channel layer, wherein the first channel layer comprises an oxide semiconductor layer; and
a second transistor disposed on the peripheral region and comprising a second channel layer, wherein the second channel layer comprises a silicon semiconductor layer;
wherein a first ratio is a ratio of a first channel width of the first channel layer to the first channel length of the first channel layer, and a second ratio is a ratio of a second channel width of the second channel layer to a second channel length of the second channel layer;
wherein the first ratio is greater than or equal to 0.4 and less than or equal to 4.5, and the second ratio is greater than or equal to 0.05 and less than or equal to 0.8.
2. The display device of claim 1 , wherein the first ratio is greater than or equal to 0.75 and less than or equal to 2.5.
3. The display device of claim 2 , the first ratio is greater than or equal to 1 and less than or equal to 1.5.
4. The display device of claim 1 , wherein the second ratio is greater than or equal to 0.09 and less than or equal to 0.45.
5. The display device of claim 4 , wherein the second ratio than or equal to 0.3 and less than or equal to 0.45.
6. The display device of claim 1 , wherein the first ratio is greater than or equal to 0.75 and less than or equal to 2.5 and the second ratio is greater than or equal to 0.09 and less than or equal to 0.45.
7. The display device of claim 6 , wherein the first ratio is greater than or equal to 1 and less than or equal to 2.5 and the second ratio is greater than or equal to 0.09 and less than or equal to 0.45.
8. The display device of claim 6 , wherein the first ratio is greater than or equal to 0.75 and less than or equal to 1.5 and the second ratio is greater than or equal to 0.3 and less than or equal to 0.45.
9. The display device of claim 1 , wherein the first transistor further comprises a first gate electrode comprising a first overlapping area, the first overlapping area and the first channel layer overlap, the second transistor further comprises a second gate electrode comprising a second overlapping area, the second overlapping area and the second channel layer overlap, and the first overlapping area is larger than the second overlapping area.
10. The display device of claim 1 , wherein the oxide semiconductor layer is an IGZO layer.
11. The display device of claim I, wherein the silicon semiconductor layer is a low temperature polysilicon layer.
12. The display device of claim 1 , wherein the first transistor electrically connects to the second transistor.
13. The display device of claim 1 , wherein the first transistor further comprises a first gate electrode disposed below the first channel layer.
14. The display device of claim 1 , wherein the second transistor further comprises a second gate electrode disposed above the second channel layer.
15. The display device of claim 1 , wherein the first transistor further comprises a first source electrode and a first drain electrode, and the first channel length is a minimum distance between the first source electrode and the first drain electrode.
16. The display device of claim 1 , further comprising a scan line electrically connecting to the first transistor, wherein the scan line extends along a first direction, the first transistor further comprises a first source electrode and a first drain electrode, the first source electrode has a first source width along a second direction substantially vertical to the first direction, the first drain electrode has a first drain width along the second direction, and the first channel width is an average width of the first source width and the first drain width.
17. The display device of claim 1 , wherein the second transistor further comprises a second source electrode and a second drain electrode, the second source electrode and the second drain electrode electrically connect to the second channel layer through contact vias, and the second channel width is a maximum with of the contact vias.
18. The display device of claim 1 , wherein the second transistor further comprises a second source electrode and a second drain electrode, the second source electrode and the second drain electrode electrically connect to the second channel layer through contact vias, and the second channel length is a minimum distance between the contact vias.