Dual-input analog-to-digital converter for improved receiver gain control
A latency associated with a receiver circuit, e.g., radio receiver circuit, can be reduced by applying digital data from an analog signal received by a receiver, e.g., a radio receiver, to an automatic gain control circuit without first using a decimation and digital filtering process, which can minimize or eliminate significant latency associated with the decimation and filtering process.
1. An analog-to-digital converter (ADC) circuit comprising:
a loop filter circuit including a first input configured to receive a first representation of an input signal and a second input configured to receive a feedback signal;
a quantizer circuit including:
at least one input configured to receive an output of the loop filter circuit and configured to receive a second representation of the input signal that bypasses the loop filter circuit;
an AGC control output, coupled to an input of an automatic gain control (AGC) circuit to establish a gain parameter using a quantization of the second representation of the input signal that bypasses the loop filter circuit; and
a quantizer signal output, coupled to an input of a decimation circuit to provide a quantized signal using a quantization of a difference between the first representation of an input signal and the feedback signal; and
a digital to analog converter (DAC) circuit configured to receive the quantizer signal output and provide the feedback signal to the second input of the loop filter circuit.
2. The ADC circuit of claim 1 , wherein the input of the ADC is coupled to the at least one input of the quantizer circuit such that the first representation of the input signal and the second representation of the input signal are the same representation of the input signal.
3. The ADC circuit of claim 1 , wherein the input of the loop filter circuit is configured to receive an output one of a baseband filter and a programmable gain amplifier circuit, and wherein the at least one input of the quantizer circuit is coupled to one of the output of the baseband filter and an internal node of the baseband filter.
4. The ADC circuit of claim 1 , wherein the input of the loop filter circuit is configured to receive an output one of a baseband filter and a programmable gain amplifier circuit, and wherein the at least one input of the quantizer circuit is configured to receive an output of a mixer circuit.
5. The ADC circuit of claim 1 , wherein the input of the AGC circuit is a first input, and wherein the decimation circuit includes an output coupled to a second input of the AGC circuit.
6. The ADC circuit of claim 1 , wherein the ADC includes a continuous-time delta-sigma ADC.
7. The ADC circuit of claim 1 , wherein the at least one first input of the quantizer circuit includes a first input and a second input, and wherein the first input is configured to receive an output of the loop filter circuit and the second input is configured to receive the second representation of the input signal that bypasses the loop filter circuit.
8. A radiofrequency (RF) receiver circuit to couple to an antenna to receive an RF input signal, the RF receiver circuit comprising:
an analog-to-digital converter (ADC) circuit coupled to an output of one of a baseband filter circuit and a programmable gain amplifier circuit, the ADC circuit including:
a loop filter circuit including a first input configured to receive a feedback signal and a second input configured to receive the output of one of the baseband filter circuit and the programmable gain amplifier circuit;
a quantizer circuit including:
at least one input configured to receive an output of the loop filter circuit and configured to receive a representation of the input signal that bypasses the loop filter circuit;
an AGC control output, coupled to an input of an automatic gain control (AGC) circuit to establish a gain parameter using a quantization of the representation of the input signal that bypasses the loop filter circuit; and
a quantizer signal output, coupled to an input of a decimation circuit to provide a quantized signal using a quantization of a difference between the representation of the RF input signal and the feedback signal;
a digital to analog converter (DAC) circuit configured to receive the quantizer signal output and provide the feedback signal to the first input of the loop filter circuit.
9. The RF receiver circuit of claim 8 , wherein the first input of the loop filter circuit is coupled to the at least one input of the quantizer circuit.
10. The RF receiver circuit of claim 8 , wherein the at least one input of the quantizer circuit is coupled to one of the output of the baseband filter, the output of the programmable gain amplifier circuit, and an internal node of the baseband filter.
11. The RF receiver circuit of claim 8 , wherein the at least one input of the quantizer circuit is configured to receive the output of a mixer circuit.
12. The RF receiver circuit of claim 8 , wherein the input of the AGC circuit is a first input, and wherein the decimation circuit includes an output coupled to a second input of the AGC circuit.
13. The RF receiver circuit of claim 8 , further comprising:
a mixer circuit, wherein the mixer circuit includes an I/Q mixer circuit, wherein the output of the mixer circuit includes a first output and a second output, wherein the first output provides an in-phase (I) signal path, wherein the second output provides a quadrature-phase (Q) signal path, and wherein the receiver includes respective I/Q channels.
14. The RF receiver circuit of claim 8 , wherein the at least one first input of the quantizer circuit includes a first input and a second input, and wherein the first input is configured to receive an output of the loop filter circuit and the second input is configured to receive the representation of the input signal that bypasses the loop filter circuit.
15. The RF receiver circuit of claim 8 , wherein the ADC includes a continuous-time delta-sigma ADC.
16. A method for radio receiver gain control, the method comprising:
receiving a radiofrequency (RF) signal;
generating a first representation of the RF signal;
applying the first representation of the RF signal to a first input of a loop filter circuit of an analog-to-digital circuit (ADC);
applying an output of the loop filter circuit to at least one input of a quantizer circuit of the ADC, generating a first quantized digital output, and applying the first quantized digital output to a decimation and digital filter circuit;
applying a second representation of the RF signal to the at least one input of the quantizer circuit of the ADC and generating a second quantized digital output; and
applying the second quantized digital output to an automatic gain control circuit.
17. The method of claim 16 , wherein applying a second representation of the RF signal to the at least one input of the quantizer of the ADC and generating a second quantized digital output includes:
applying one of the output of the baseband filter and an internal node of the baseband filter to the at least one input of the quantizer of the ADC and generating a second quantized digital output.
18. The method of claim 16 , wherein applying a second representation of the RF signal to the at least one input of the quantizer of the ADC and generating a second quantized digital output includes:
applying an output of a mixer circuit to the at least one input of the quantizer of the ADC and generating a second quantized digital output.
19. The method of claim 16 , wherein applying a second representation of the RF signal to the at least one input of the quantizer of the ADC and generating a second quantized digital output includes:
applying an output of a programmable gain amplifier circuit to the at least one input of the quantizer of the ADC and generating a second quantized digital output.
20. The method of claim 16 , wherein the first representation of the RF signal applied to the loop filter and the second representation of the RF signal are the same representation of the RF signal.
21. The RF receiver circuit of claim 8 , further comprising:
a low noise amplifier (LNA) circuit including an input coupled to the antenna and an output.
22. The RF receiver circuit of claim 8 , further comprising:
a mixer circuit including a first input configured to receive the output of a low noise amplifier (LNA) circuit, a second input configured to receive a local oscillator signal, and an output, the mixer circuit configured to mix the output of the LNA circuit received at the first input with the local oscillator signal received at the second input to provide an intermediate frequency signal at a lower frequency than the received RF signal at the output.
23. The RF receiver circuit of claim 8 , further comprising:
the baseband filter circuit including an input configured to receive the output of a mixer circuit; and
an automatic gain control (AGC) circuit including an input and at least one output coupled to and configured to establish a gain parameter of at least one of a low noise amplifier (LNA) circuit, the mixer circuit, and the baseband filter circuit.