Memory system and method of controlling nonvolatile memory
According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less than a second threshold. The first refreshing includes reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block.
1. A memory system comprising:
a nonvolatile memory including a plurality of blocks, each of the blocks including a plurality of word lines and being a unit for erasing of data, each of the word lines connecting a plurality of memory cells and being a unit for programming of data, the memory cells being cells that require erasing of data before being programmed; and
a controller circuit configured to:
instruct the nonvolatile memory to program a plurality of first memory cells connected to a first word line included in a first block, wherein programming the first memory cells includes a verify process to verify that each of the first memory cells has a certain threshold voltage; and
without instructing the nonvolatile memory to erase data from the first block,
instruct the nonvolatile memory to perform first refreshing, the first refreshing including programming at least one second memory cell among the first memory cells, wherein programming the at least one secondary memory cell in the first refreshing does not include a verify process to verify that the second memory cell has a certain threshold voltage.
2. The memory system according to claim 1 , wherein the first refreshing includes not programming a plurality of third memory cells that are different from the second memory cell among the first memory cells.
3. The memory system according to claim 1 , wherein programming the first memory cells is performed with a first number of programming pulses, programming the second memory cell in the first refreshing is performed with a second number of programming pulses, and the second number is smaller than the first number.
4. The memory system according to claim 3 , wherein the second number is one.
5. The memory system according to claim 1 , wherein,
when the second memory cell has been programmed using a threshold voltage belonging to a first distribution, the second memory cell is programmed in the first refreshing using a first correction amount, and
when the second memory cell has been programmed using a threshold voltage belonging to a second distribution, the second memory cell is programmed in the first refreshing using a second correction amount.
6. The memory system according to claim 1 , wherein the nonvolatile memory is a flash memory having a three-dimensional structure.
7. The memory system according to claim 2 , wherein the controller circuit is further configured to specify the second memory cell and transmit a first command to the nonvolatile memory to instruct the first refreshing, the first command includes data and an address for programming the specified second memory cell and not programming the third memory cells.
8. The memory system according to claim 7 , wherein the controller circuit specifies the second memory cell based on an error correction process.
9. The memory system according to claim 7 , wherein the controller circuit specifies the second memory cell based on a distribution read process.
10. The memory system according to claim 1 , wherein the controller circuit is further configured to transmit a first command to the nonvolatile memory to instruct the first refreshing, the first command specifies first information that includes an address of the first memory cells and second information that includes data for programming the first memory cells, and
the nonvolatile memory further includes a second controller circuit configured to:
when the first command is received, specify positions of the first memory cells inside the nonvolatile memory based on the first information;
specify the second memory cell among the specified first memory cells; and
execute the first refreshing for the specified second memory cell by using the second information.
11. The memory system according to claim 1 , wherein the controller circuit instructs the first refreshing when a number of error bits in the first block is larger than a first threshold.
12. The memory system according to claim 1 , wherein the controller circuit instructs the first refreshing when a number of times of executing error correction on the first block is larger than a first threshold.
13. The memory system according to claim 1 , wherein the controller circuit instructs the first refreshing when a time from the programming to the first memory cells or a time from a previous first refreshing is longer than a first threshold.
14. The memory system according to claim 1 , wherein the controller circuit instructs the first refreshing when a number of times of reading data on the first block is larger than a first threshold.
15. The memory system according to claim 1 , wherein the controller circuit is further configured to instruct the nonvolatile memory to perform second refreshing, the second refreshing including moving data in the first block to a second block that is different from the first block.
16. The memory system according to claim 15 , wherein the controller circuit instructs the first refreshing when a number of error bits in the first block is larger than a first threshold and instructs the second refreshing when the number of error bits in the first block is larger than a second threshold, the second threshold is larger than the first threshold.
17. The memory system according to claim 16 , wherein the controller circuit instructs the second refreshing when a number of times of executing the first refreshing is larger than a first threshold.
18. A method of controlling a nonvolatile memory, the nonvolatile memory including a plurality of blocks, each of the blocks including a plurality of word lines and being a unit for erasing of data, each of the word lines connecting a plurality of memory cells and being a unit for programming of data, the memory cells being cells that require erasing of data before being programmed, the method comprising:
instructing the nonvolatile memory to program a plurality of first memory cells connected to a first word line included in a first block, wherein programming the first memory cells includes a verify process to verify that each of the first memory cells has a certain threshold voltage; and
without instructing the nonvolatile memory to erase data from the first block,
instructing the nonvolatile memory to perform first refreshing, the first refreshing including programming at least one second memory cell among the first memory cells, wherein programming the at least one secondary memory cell in the first refreshing does not include a verify process to verify that the second memory cell has a certain threshold voltage.
19. The method according to claim 18 , wherein the first refreshing includes not programming a plurality of third memory cells that are different from the second memory cell among the first memory cells.