IP Library Granted Patent US 10,013,180
Granted Patent B1
US 10,013,180 · App. 15/482,051 · Granted Jul 3, 2018

Operating methods of nonvolatile memory device and data storage device including the same

Inventor: Dong Sop Lee (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
G06F3/061G06F3/0638G06F3/0656G06F3/0659G06F3/0679G11C7/10G11C7/22G11C8/06G11C8/10
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,013,180
App. No.
15/482,051
Granted
Jul 3, 2018
Kind
B1
Abstract

A method for operating a data storage device including a nonvolatile memory device and a controller which controls the nonvolatile memory device includes the controller transmitting to the nonvolatile memory device one of a command, an address, seed data and data via a input/output line and first, second and third control signals via corresponding signal lines; and the nonvolatile memory device receiving any one of the transmitted command, the address, the seed data and the data depending on at least two of the first, second and third control signals.

Claims (32)

1. A method for operating a data storage device including a nonvolatile memory device and a controller, the method comprising:

generating, by the controller, seed data and transmitting to the nonvolatile memory device one of a command, an address, the seed data and data via a input/output line and first, second and third control signals via corresponding signal lines; and

receiving, by the nonvolatile memory device, any one of the transmitted command, the address, the seed data and the data depending on at least two of the first, second and third control signals,

wherein the nonvolatile memory device randomizes or de-randomizes the data based on the seed data transmitted from the controller.

2. The method according to claim 1 , wherein the nonvolatile memory device receives the seed data when the first control signal and the second control signal are enabled and the third control signal toggles.

3. The method according to claim 1 , wherein the nonvolatile memory device receives the command when the first control signal is enabled and the second control signal is disabled.

4. The method according to claim 1 , wherein the nonvolatile memory device receives the address when the first control signal is disabled and the second control signal is enabled.

5. The method according to claim 1 , wherein the nonvolatile memory device receives the data when the first control signal and the second control signal are disabled and the third control signal toggles.

6. The method according to claim 1 , wherein the first control signal is a command latch enable signal, the second control signal is an address latch enable signal, and the third control signal is a data strobe signal.

7. A method for operating a nonvolatile memory device, comprising:

receiving input/output signals including a command, an address, seed data and data through input/output lines from a controller;

receiving a first control signal and a second control signal;

identifying the input/output signal as the seed data when the first control signal and the second control signal are enabled; and

randomizing or de-randomizing the data based on the seed data received from the controller.

8. The method according to claim 7 ,

further comprising receiving a third control signal,

wherein the receiving of the input/output signals includes receiving the seed data each time the third control signal toggles.

9. The method according to claim 8 , wherein the first control signal is a command latch enable signal, the second control signal is an address latch enable signal, and the third control signal is a data strobe signal.

10. The method according to claim 7 , further comprising identifying the input/output signal as the command when the first control signal is enabled and the second control signal is disabled.

11. The method according to claim 7 , further comprising identifying the input/output signal as the address when the first control signal is disabled and the second control signal is enabled.

12. The method according to claim 7 , further comprising identifying the input/output signal as the data when the first control signal and the second control signal are disabled.

13. The method according to claim 12 ,

further comprising receiving a third control signal,

wherein the receiving of the input/output signals includes receiving the data each time the third control signal toggles.

14. A nonvolatile memory device comprising:

an input/output buffer block suitable for receiving input/output signals including one or more of a command, an address, data and seed data based on a combination of first to third control signals from a controller;

a seed storage block suitable for storing the seed data when the first and second control signals are enabled; and

a randomization/de-randomization block suitable for randomizing the data to be stored in memory cells or de-randomizing the data read out from the memory cells based on the seed data received from the controller.

15. The nonvolatile memory device according to claim 14 , wherein the input/output buffer block receives the seed data each time the third control signal toggles.

16. The nonvolatile memory device according to claim 14 , wherein the input/output buffer block receives the command when the first control signal is enabled and the second control signal is disabled.

17. The nonvolatile memory device according to claim 14 , wherein the input/output buffer block receives the address when the first control signal is disabled and the second control signal is enabled.

18. The nonvolatile memory device according to claim 14 , wherein the input/output buffer block receives one data each time the third control signal toggles when the first control signal and the second control signal are disabled.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2017
From: LEE, DONG SOP
To: SK HYNIX INC.
Reel/Frame 042193/0377 →
Priority Claims (1)
KR 10-2016-0182678 · Dec 29, 2016 · national
Cited By (1)
US 12,669,962