Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values
A mechanism is described for facilitating fast data operations and for facilitating a finite state machine for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.
1. An apparatus comprising:
a graphics processor comprising computation circuitry, the graphics processor to:
identify a plurality of frequently-used data values (FDVs), wherein the plurality of FDVs are any of number values 0, 0.5 or 1;
generate an FDV configuration comprising the plurality of FDVs;
detect input data to be used in computational tasks by the computation circuitry of the graphics processor;
in response to detecting the input data, assign the FDV configuration to the input data to reduce mathematical operations associated with one or more FDVs of the plurality of FDVs;
identify, based on the FDV configuration, occurrence in the input data of the one or more FDVs of the plurality of FDVs;
push the one or more FDVs to bypass the computational tasks; and
implement a finite state machine (FSM) to provide a common primitive for convolution and full connection computation for the computational tasks by the computation circuitry of the graphics processor, wherein the graphics processor is further to implement the FSM to represent a mathematical model of computation that is an abstract machine, and wherein the FSM is to combine memory read accesses and is to merge two or more of the mathematical operations.
2. The apparatus of claim 1 , wherein the graphics processor is further to:
determine one or more non-FDVs from the input data; and
set the one or more non-FDVs on a computational path comprising the computational tasks, the computational path to pass through the computation circuitry.
3. The apparatus of claim 2 , wherein the mathematical operations comprise at least one member selected from the group consisting of addition, subtraction, multiplication, or division.
4. The apparatus of claim 1 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.
5. A method comprising:
identifying, by a graphics processor comprising computation circuitry, a plurality of frequently-used data values (FDVs), wherein the plurality of FDVs are any of number values 0, 0.5 or 1;
generating an FDV configuration comprising the plurality of FDVs;
detecting, by the graphics processor, input data to be used in computational tasks by the computation circuitry of the graphics processor;
in response to detecting the input data, assigning the FDV configuration to the input data to reduce mathematical operations associated with one or more FDVs of the plurality of FDVs;
identifying, based on the FDV configuration, occurrence in the input data of the one or more FDVs of the plurality of FDVs;
pushing the one or more FDVs to bypass the computational tasks; and
implementing a finite state machine (FSM) to provide a common primitive for convolution and full connection computation for the computational tasks by the computation circuitry of the graphics processor, wherein the graphics processor is further to implement the FSM to represent a mathematical model of computation that is an abstract machine, and wherein the FSM is to combine memory read accesses and is to merge two or more of the mathematical operations.
6. The method of claim 5 , further comprising:
determining one or more non-FDVs from the input data; and
setting the one or more non-FDVs on a computational path comprising the computational tasks, the computational path to pass through the computation circuitry.
7. The method of claim 6 , wherein the mathematical operations comprise at least one member selected from the group consisting of addition, subtraction, multiplication, or division.
8. The method of claim 5 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.
9. At least one non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
identifying, by a graphics processor of the computing device, a plurality of frequently-used data values (FDVs), wherein the plurality of FDVs are any of number values 0, 0.5 or 1;
generating an FDV configuration comprising the plurality of FDVs;
detecting, by the graphics processor, input data to be used in computational tasks by the graphics processor;
in response to detecting the input data, assigning the FDV configuration to the input data to reduce mathematical operations associated with one or more FDVs of the plurality of FDVs;
identifying, based on the FDV configuration, occurrence in the input data of the one or more FDVs of the plurality of FDVs;
pushing the one or more FDVs to bypass the computational tasks; and
implementing a finite state machine (FSM) to provide a common primitive for convolution and full connection computation for the computational tasks by the graphics processor, wherein the graphics processor is further to implement the FSM to represent a mathematical model of computation that is an abstract machine, and wherein the FSM is to combine memory read accesses and is to merge two or more of the mathematical operations.
10. The non-transitory machine-readable medium of claim 9 , wherein the instructions, when executed by the computing device, further cause the computing device to perform operations comprising:
determining one or more non-FDVs from the input data; and
setting the one or more non-FDVs on a computational path comprising the computational tasks, the computational path to pass through the computing device.
11. The non-transitory machine-readable medium of claim 10 , wherein the mathematical operations comprise at least one member selected from the group consisting of addition, subtraction, multiplication, or division.
12. The non-transitory machine-readable medium of claim 9 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.
13. A system comprising:
a memory; and
a graphics processor communicably coupled to the memory, the graphics processor comprising computation circuitry and the graphics processor to:
identify a plurality of frequently-used data values (FDVs), wherein the plurality of FDVs are any of number values 0, 0.5 or 1;
generate an FDV configuration comprising the plurality of FDVs;
detect input data to be used in computational tasks by the computation circuitry of the graphics processor;
in response to detecting the input data, assign the FDV configuration to the input data to reduce mathematical operations associated with one or more FDVs of the plurality of FDVs;
identify, based on the FDV configuration, occurrence in the input data of the one or more FDVs of the plurality of FDVs;
push the one or more FDVs to bypass the computational tasks; and
implement a finite state machine (FSM) to provide a common primitive for convolution and full connection computation for the computational tasks by the computation circuitry of the graphics processor, wherein the graphics processor is further to implement the FSM to represent a mathematical model of computation that is an abstract machine, and wherein the FSM is to combine memory read accesses and is to merge two or more of the mathematical operations.
14. The system of claim 13 , wherein the graphics processor is further to:
determine one or more non-FDVs from the input data; and
set the one or more non-FDVs on a computational path comprising the computational tasks, the computational path to pass through the computation circuitry.
15. The system of claim 14 , wherein the mathematical operations comprise at least one member selected from the group consisting of addition, subtraction, multiplication, or division.
16. The system of claim 13 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.