Global coarse baseline correction charge injection
A global coarse baseline correction charge injection circuit comprises: an output capacitor, a slew rate control circuit, a current generator, a first current mirror, and a second current mirror. The output capacitor is configured to store a global coarse baseline correction charge. The slew rate control circuit is configured to receive a modulated voltage, a positive input current, and a negative input current as inputs, and provide a proportional-to-supply-voltage slew-rate controlled voltage as an output voltage to charge the output capacitor. The current generator is configured to receive a supply voltage as an input and provide a proportional-to-supply-voltage (PTSV) current as an output. The first current mirror is configured to mirror the PTSV current to the slew rate control circuit as the positive input current. The second current mirror is configured to mirror the PTSV current to the slew rate control circuit as the negative input current.
1. A global coarse baseline correction charge injection circuit, said circuit comprising:
an output capacitor configured as a dedicated capacitor used to store a global coarse baseline correction charge; and
a slew rate control circuit configured to receive a modulated voltage, a positive input current, and a negative input current as inputs and provide a proportional-to-supply-voltage slew-rate controlled voltage as an output voltage to charge said output capacitor with said global coarse baseline correction charge,
wherein said slew rate control circuit is integrator based and comprises:
a first integrator configured to integrate said negative input current into said output voltage during a first half cycle of operation of said slew rate control circuit; and
a second integrator to integrate said positive input current into said output voltage during a second half cycle of operation of said slew rate control circuit;
a first pre-charge circuit configured to pre-charge an input of said first integrator prior to said first half cycle of operation; and
a second pre-charge circuit configured to pre-charge an input of said second integrator prior to said second half cycle of operation.
2. The global coarse baseline correction charge injection circuit of claim 1 , further comprising:
a plurality of coarse baseline correction output current mirrors coupled with said output capacitor and configured to mirror out local copies of said global coarse baseline correction charge to each of a plurality of charge integrators in a processing system for a capacitive sensing input device.
3. The global coarse baseline correction charge injection circuit of claim 1 , wherein said first integrator and said second integrator share a feedback capacitor, and wherein said feedback capacitor is a variable capacitor.
4. The global coarse baseline correction charge injection circuit of claim 1 , wherein said output capacitor comprises a variable capacitor.
5. The global coarse baseline correction charge injection circuit of claim 1 , wherein said global coarse baseline correction charge is ratio-metric to the modulated voltage.
6. The global coarse baseline correction charge injection circuit of claim 1 , further comprising:
a current generator configured to receive a supply voltage as an input and provide a proportional-to-supply-voltage current as an output;
a first current mirror configured to mirror said proportional-to-supply-voltage current to said slew rate control circuit as said positive input current; and
a second current mirror configured to mirror said proportional-to-supply-voltage current to said slew rate control circuit as said negative input current.
7. The global coarse baseline correction charge injection circuit of claim 6 , wherein said current generator comprises a low temperature coefficient trimmable resistor, whose process dependent variation can be trimmed out.
8. A processing system for a capacitive sensing input device, said processing system, comprising:
a charge integrator comprising an input configured to switchably couple with a capacitive sensor electrode, said input configured to receive a charge from said capacitive sensor electrode for integration;
a local coarse baseline correction capacitor coupled with said input and configured to store and provide a local coarse baseline correction charge to offset a background capacitance of said capacitive sensor electrode; and
a global coarse baseline correction charge injection circuit, switchably coupled to the input of the charge integrator, and configured to generate a global coarse baseline correction charge and to mirror out a copy of said global coarse baseline correction charge to said input of said charge integrator, said circuit comprising:
an output capacitor configured as a dedicated capacitor used to store said global coarse baseline correction charge;
a slew rate control circuit configured to receive a modulated voltage, a positive input current, and a negative input current as inputs and provide a proportional-to-supply-voltage slew-rate controlled voltage as an output voltage to charge said output capacitor with said global coarse baseline correction charge,
wherein the slew rate control circuit is integrator based and comprises:
a first integrator configured to integrate said positive input current into said output voltage during a first half cycle of operation of said slew rate control circuit, and
a second integrator to integrate said negative input current into said output voltage during a second half cycle of operation of said slew rate control circuit,
wherein said first integrator and said second integrator share a feedback capacitor; and
a coarse baseline correction current mirror coupled with said output capacitor and configured to mirror out said copy of said global coarse baseline correction charge.
9. The processing system of claim 8 , wherein said feedback capacitor is a variable capacitor.
10. The processing system of claim 8 , wherein said global coarse baseline correction charge injection circuit further comprises:
a first pre-charge circuit configured to pre-charge an input of said first integrator prior to said first half cycle of operation; and
a second pre-charge circuit configured to pre-charge an input of said second integrator prior to said second half cycle of operation.
11. The processing system of claim 8 , wherein said output capacitor comprises a variable capacitor.
12. The processing system of claim 8 , wherein said global coarse baseline correction charge is ratio-metric to said modulated voltage.
13. A capacitive sensing input device comprising:
a capacitive sensor electrode;
a charge integrator comprising an input configured to switchably couple with said capacitive sensor electrode, said input configured to receive a charge from said capacitive sensor electrode for integration;
a local coarse baseline correction capacitor coupled with said input and configured to store and provide a local coarse baseline correction charge to offset a background capacitance of said capacitive sensor electrode;
a global coarse baseline correction charge injection circuit, switchably coupled to the input of the charge integrator, and configured to generate a global coarse baseline correction charge and to mirror out a copy of said global coarse baseline correction charge to said input of said charge integrator, said circuit comprising:
an output capacitor configured as a dedicated capacitor used to store said global coarse baseline correction charge;
a slew rate control circuit configured to receive a modulated voltage, a positive input current, and a negative input current as inputs and provide a proportional-to-supply-voltage slew-rate controlled voltage as an output voltage to charge said output capacitor with said global coarse baseline correction charge,
wherein said slew rate control circuit is integrator based and comprises:
a first integrator configured to integrate said positive input current into said output voltage during a first half cycle of operation of said slew rate control circuit, and
a second integrator to integrate said negative input current into said output voltage during a second half cycle of operation of said slew rate control circuit, and
wherein said global coarse baseline correction charge injection circuit comprises:
a first pre-charge circuit configured to pre-charge an input of said first integrator prior to said first half cycle of operation, and
a second pre-charge circuit configured to pre-charge an input of said second integrator prior to said second half cycle of operation; and
a coarse baseline correction output current mirror coupled with said output capacitor and configured to mirror out said copy of said global coarse baseline correction charge.
14. The capacitive sensing input device of claim 13 , wherein said first integrator and said second integrator share a feedback capacitor, and wherein said feedback capacitor is a variable capacitor.
15. The capacitive sensing input device of claim 13 , wherein said global coarse baseline correction charge is ratio-metric to said modulated voltage.