Embedded PMOS-trigger silicon controlled rectifier (SCR) with suppression rings for electro-static-discharge (ESD) protection
An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure with a P+ anode/source within a center N-well, a P-substrate, and an outer N-well that connects to a cathode using N+ well taps. The P+ anode/source is both the source of the triggering PMOS transistor and the anode of the SCR. A trigger circuit drives the gate of the triggering PMOS transistor low, turning it on to charge the P+ drain. Since the P+ drain straddles the well boundary, making physical contact with both the center N-well and the P-substrate, holes flow into the P-substrate. The P+ drain is located near guard rings that suppress latch-up. The holes from the P+ drain flood the region under the guard rings, temporarily weakening their effect and reducing the trigger voltage.
1. An Electro-Static-Discharge (ESD) protection structure comprising:
a center N-well formed in a P-substrate;
a P+ anode/source formed in the center N-well, the P+ anode/source connected to an anode terminal for receiving an ESD pulse;
a P+ drain formed along an edge of the center N-well, wherein the P+ drain makes physical contact with both the center N-well and the P-substrate;
a P-channel Metal-Oxide-Semiconductor (PMOS) transistor formed in the center N-well, the PMOS transistor having a gate driven by an inverse trigger signal that is driven low during the ESD pulse, the gate controlling conduction in a channel between the P+ anode/source and the P+ drain;
an outer N-well that has an N+ well tap that connects to a cathode terminal for the ESD pulse;
a guard ring located between the center N-well and the outer N-well, the guard ring for reducing susceptibility to latch-up, and
a second P+ drain formed along an edge of the center N-well, wherein the second P+drain makes physical contact with both the center N-well and the P-substrate; and
a second PMOS transistor formed in the center N-well, the second PMOS transistor having a second gate driven by the inverse trigger signal that is driven low during the ESD pulse, the second gate controlling conduction in a second channel between the P+ anode/source and the second P+ drain;
wherein the P+ anode/source is shared by the PMOS transistor and the second PMOS transistor.
2. The ESD protection structure of claim 1 wherein the PMOS transistor turns on during the ESD pulse, conducting holes from the P+ anode/source to the P+ drain;
wherein the P+ drain injects holes into the P-substrate near the guard ring;
wherein the holes injected by the P+ drain temporarily suppress an effect of the guard ring while the PMOS transistor is turned on.
3. The ESD protection structure of claim 2 wherein a trigger voltage of the ESD protection structure is reduced when the PMOS transistor is turned on to inject holes into the P-substrate near the guard ring, the trigger voltage having a larger value when the PMOS transistor is turned off than when the PMOS transistor is turned on.
4. The ESD protection structure of claim 3 wherein a Silicon-Controlled Rectifier (SCR) is formed by the P+ anode/source, the center N-well, the P-substrate, and the outer N-well.
5. The ESD protection structure of claim 4 wherein the SCR turns on to conduct when the trigger voltage is reached.
6. The ESD protection structure of claim 1 wherein the guard ring comprises:
a P+ guard ring; and
an N+ guard ring.
7. The ESD protection structure of claim 6 wherein the guard ring completely surrounds the center N-well.
8. The ESD protection structure of claim 6 wherein the P+ guard ring and the N+ guard ring are electrically connected to each other.
9. The ESD protection structure of claim 1 further comprising:
a trigger circuit that receives the ESD pulse, the trigger circuit generating the inverse trigger signal, the trigger circuit driving the inverse trigger signal low when the trigger circuit detects the ESD pulse.
10. The ESD protection structure of claim 9 wherein the trigger circuit comprises:
a capacitor coupled between the anode terminal and a sense node;
a resistor coupled between the sense node and the cathode terminal; and
an inverter having the sense node as an input and an output driving the inverse trigger signal.
11. The ESD protection structure of claim 1 further comprising:
a center N+ tap formed within the center N-well.
12. The ESD protection structure of claim 11 further comprising:
an anode resistor, coupled between the center N+ tap and the anode terminal.
13. The ESD protection structure of claim 1 further comprising:
an offset center N+ tap formed within the center N-well, for connecting to the anode terminal directly or through an anode resistor.
14. An Electro-Static-Discharge (ESD) protection structure comprising:
a center N-well formed in a P-substrate;
a P+ anode/source formed in the center N-well, the P+ anode/source connected to an anode terminal for receiving an ESD pulse;
a P+ drain formed along an edge of the center N-well, wherein the P+ drain makes physical contact with both the center N-well and the P-substrate;
a P-channel Metal-Oxide-Semiconductor (PMOS) transistor formed in the center N-well, the PMOS transistor having a gate driven by an inverse trigger signal that is driven low during the ESD pulse, the gate controlling conduction in a channel between the P+ anode/source and the P+ drain;
an outer N-well that has an N+ well tap that connects to a cathode terminal for the ESD pulse;
a guard ring located between the center N-well and the outer N-well, the guard ring for reducing susceptibility to latch-up;
a second P+ drain formed along an edge of the center N-well, wherein the second P+drain makes physical contact with both the center N-well and the P-substrate;
a second P+ anode/source formed in the center N-well, the second P+ anode/source connected to the anode terminal that receives the ESD pulse; and
a second PMOS transistor formed in the center N-well, the second PMOS transistor having a second gate driven by the inverse trigger signal that is driven low during the ESD pulse, the second gate controlling conduction in a second channel between the second P+ anode/source and the second P+ drain.
15. The ESD protection structure of claim 14 further comprising:
a center N+ tap formed within the center N-well, for connecting to the anode terminal directly or through an anode resistor;
wherein the center N+ tap is formed between the P+ anode/source and the second P+anode/source.
16. The ESD protection structure of claim 14 wherein during a normal operation mode, the cathode terminal is connected to a ground supply and the anode terminal is connected to a power supply.
17. An input protection device comprising:
a Silicon-Controlled Rectifier (SCR) that comprises a PNPN structure that comprises:
a P+ anode/source connected to a first terminal for receiving an electrical shock pulse;
a center N-well;
a P-substrate that surrounds the center N-well;
an outer N-well connected to a second terminal for receiving the electrical shock pulse;
a guard ring placed in the P-substrate between the center N-well and the outer N-well;
a p-channel transistor formed in the center N-well;
a P+ drain formed to straddle a boundary between the center N-well and the P-substrate;
a gate for controlling a channel in the p-channel transistor, the channel carrying current from the P+ anode/source to the P+ drain; and
a trigger circuit that receives the electrical shock pulse and generates a low-going signal to the gate when the electrical shock pulse is detected;
wherein the p-channel transistor turns on when the electrical shock pulse is detected, the p-channel transistor charging the P+ drain and causing the P+ drain to inject electrical carriers into the P-substrate;
a second P+ drain formed along an edge of the center N-well, wherein the second P+ drain makes physical contact with both the center N-well and the P-substrate; and
a second p-channel transistor formed in the center N-well, the second p-channel transistor having a second gate driven by the low-going signal that is generated by the electrical shock pulse, the second gate controlling conduction in a second channel between the P+ anode/source and the second P+ drain;
wherein the P+ anode/source is shared by the p-channel transistor and the second p-channel transistor,
whereby the SCR turns on at a lower voltage when the p-channel transistor is turned on to inject the electrical carriers that temporarily suppress an effect of the guard ring.