High-density neuromorphic computing element
A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.
1. A neuromorphic device, comprising:
a substrate, the substrate being substantially planar;
a first floating-gate transistor on the substrate, the first floating-gate transistor having:
a channel;
a floating gate; and
a control gate; and
a second floating-gate transistor, vertically stacked on the first floating-gate transistor in a stacking direction, the second floating-gate transistor having:
a channel;
a floating gate; and
a control gate directly connected to the control gate of the first floating-gate transistor,
the neuromorphic device having:
a gate contact connected to:
the control gate of the first floating-gate transistor; and
the control gate of the second floating-gate transistor;
a first source-drain contact connected to a first end of the channel of the first floating-gate transistor;
a second source-drain contact connected to a second end, which is opposite the first end, of the channel of the first floating-gate transistor and to a first end of the channel of the second floating-gate transistor; and
a third source-drain contact connected to a second end of the channel of the second floating-gate transistor,
wherein the second source-drain contact includes a portion extending between the floating gate of the first floating-gate transistor and the floating gate of the second floating-gate transistor such that the floating gate of first floating-gate transistor, the portion of the second source-drain contact, and the floating gate of the second floating-pate transistor overlap with each other in the stacking direction.
2. The neuromorphic device of claim 1 , wherein the channel of the first floating-gate transistor and the channel of the second floating-gate transistor are parts of one continuous, vertical structure.
3. The neuromorphic device of claim 1 , wherein the neuromorphic device has:
a first number of floating-gate transistors, including the first floating-gate transistor and the second floating-gate transistor; and
a second number of source-drain contacts, including the first source-drain contact, the second source-drain contact, and the third source-drain contact,
the second number being greater than the first number by one.
4. The neuromorphic device of claim 1 , comprising sixteen floating-gate transistors including the first floating-gate transistor and the second floating-gate transistor.
5. The neuromorphic device of claim 1 , comprising thirty-two floating-gate transistors including the first floating-gate transistor and the second floating-gate transistor.
6. The neuromorphic device of claim 1 , wherein:
the first source-drain contact includes:
a first conductive path; and
a second conductive path,
the first conductive path being horizontal and having a first length, and the second conductive path being vertical and having a second length,
the second source-drain contact includes:
a third conductive path; and
a fourth conductive path,
the third conductive path being horizontal and having a third length less than the first length, and the fourth conductive path being vertical and having a fourth length less than the second length.
7. The neuromorphic device of claim 1 , wherein each of the first source-drain contact and the second source-drain contact comprises a horizontal portion, and the gate contact comprises a vertical portion in a gate contact opening penetrating:
the horizontal portion of the first source-drain contact; and
the horizontal portion of the second source-drain contact,
the neuromorphic device further comprising:
an internal sidewall spacer in the gate contact opening, to insulate the gate contact from the horizontal portion of the first source-drain contact; and
an internal sidewall spacer in the gate contact opening, to insulate the gate contact from the horizontal portion of the second source-drain contact.