Memory system and management table
View Patent ↗According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.
1. A memory device comprising:
a nonvolatile semiconductor memory;
a data buffer in which user data to be written into the nonvolatile semiconductor memory are temporarily stored;
a rechargeable power source; and
a monitoring circuit configured to:
monitor a voltage from an external power source that is external to the memory device,
assert a first signal, which causes an operation of saving the user data in the data buffer into the nonvolatile semiconductor memory to start, in response to the monitored voltage dropping to a first value, and
assert a second signal, which causes supply of the voltage from the external power source to the memory device to be stopped, in response to the monitored voltage dropping further to a second value that is lower than the first value.
2. The memory device according to claim 1 , wherein
the monitoring circuit is also configured to assert a third signal, which causes discharging of the rechargeable power source in response to the monitored voltage dropping to the second value.
3. The memory device according to claim 2 , further comprising:
a power regulator configured to generate voltage supplied to the nonvolatile semiconductor memory based on the voltage from the external power source and voltage from the rechargeable power source, wherein
in response to the generated voltage dropping to a threshold value, the first signal is deasserted, which causes the operation to stop.
4. The memory device according to claim 3 , wherein
in response to the generated voltage dropping to the threshold value, the third signal is also deasserted, which causes the discharging of the rechargeable power source to be stopped.
5. The memory device according to claim 1 , wherein
the monitoring circuit is further configured to deassert a fourth signal, which causes charging of the rechargeable power source to be stopped, in response to the monitored voltage dropping to the second value.
6. The memory device according to claim 5 , wherein
the monitoring circuit is further configured to assert the fourth signal, which causes the charging of the rechargeable power source to be started, in response to the monitored voltage rising to a third value that is lower than the second value.
7. The memory device according to claim 1 , further comprising:
a second monitoring circuit configured to monitor a voltage of the rechargeable power source, and assert a signal, which causes data transmission from or to a host to be started, in response to the monitored voltage of the rechargeable power source rising to a threshold value.
8. The memory device according to claim 1 , further comprising:
a controller configured to start the operation of saving the user data, in response to assertion of the first signal.
9. The memory device according to claim 1 , further comprising:
a switching circuit configured to select one of the voltage from the external power source and voltage from the rechargeable power source, based on assertion and deassertion of the second signal, and supply the selected voltage to the nonvolatile semiconductor memory.
10. The memory device according to claim 1 , further comprising:
a volatile memory in which management data that uniquely associate the user data with an address of the nonvolatile semiconductor memory are stored, wherein
through the operation, the management data in the volatile memory are also saved into the nonvolatile semiconductor memory.
11. The memory device according to claim 1 , wherein
assertion of the first signal also causes a read or erase operation that is being carried out in accordance with a command from a host to stop.
12. The memory device according to claim 1 , wherein
the nonvolatile semiconductor memory is a NAND flash memory.
13. The memory device according to claim 1 , wherein
the rechargeable power source includes a capacitor.