IP Library Granted Patent US 10,709,319
Granted Patent B2
US 10,709,319 · App. 15/489,588 · Granted Jul 14, 2020

System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects

Inventor: Laurent Blanquart (Westlake Village, CA)
Assignee: DePuy Synthes Products, Inc.
A61B1/051A61B1/00009A61B1/0676H01L24/17H01L25/0657H01L27/124H01L27/146H01L27/1464H01L27/1469H01L27/14601H01L27/14603H01L27/14609H01L27/14618H01L27/14634H01L27/14636H01L27/14638H01L27/14641H01L27/14643H01L27/14689H04N5/2256H04N5/378H04N5/379H04N5/3742H04N5/37455H04N5/37457H01L31/028H01L31/0296H01L31/0304H01L2924/0002H01L2924/381H04N2005/2255
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Quick Facts
Patent No.
US 10,709,319
App. No.
15/489,588
Granted
Jul 14, 2020
Kind
B2
Abstract

Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array.

Claims (36)

1. An imaging sensor comprising:

a pixel array comprising a plurality of pixel columns disposed on a first substrate, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns;

a plurality of supporting circuits disposed on a second substrate and corresponding to each of the plurality of pixel sub-columns, wherein the plurality of supporting circuits disposed on the second substrate are each only connected to one of the plurality of pixel sub-columns; and

wherein the plurality of supporting circuits are configured to independently read and process data from a corresponding pixel sub-column, and wherein pixel sub-columns within a same pixel column are read simultaneously as part of a rolling shutter.

2. The imaging sensor of claim 1 , further comprising one or more additional substrates.

3. The imaging sensor of claim 2 , wherein the one or more additional substrates are disposed remotely relative to the first substrate.

4. The imaging sensor of claim 2 , further comprising a pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate and a circuit sub-column bus for each of the plurality of supporting circuits that correspond to each of the plurality of pixel sub-columns on the one or more additional substrates.

5. The imaging sensor of claim 4 , wherein each pixel sub-column bus is at least partially superimposed relative to a corresponding circuit sub-column bus on the one or more additional substrates, wherein the first substrate and the one or more additional substrates are in a stacked configuration.

6. The imaging sensor of claim 4 , further comprising at least one interconnect connecting the pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate with a corresponding circuit sub-column bus for each of the plurality of supporting circuits on the one or more additional substrates.

7. The imaging sensor of claim 1 , wherein the imaging sensor is backside illuminated.

8. The imaging sensor of claim 1 , wherein each pixel sub-column is electronically isolated from other pixel sub-columns.

9. The imaging sensor of claim 1 , wherein a dedicated portion of the plurality of supporting circuits are dedicated to a corresponding pixel sub-column of the pixel array.

10. The imaging sensor of claim 1 , wherein reading pixel sub-columns within the same pixel column simultaneously comprises:

reading and processing data by supporting circuits corresponding to a specific pixel sub-column in parallel with supporting circuits corresponding to another pixel sub-column within the same pixel column.

11. An imaging sensor comprising:

a plurality of stacked substrates comprising a first substrate and one or more additional substrates proximal to the first substrate;

a pixel array on the first substrate comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns;

a pixel sub-column bus on the first substrate for each of the plurality of pixel sub-columns;

a plurality of supporting circuits on the one or more additional substrates, the plurality of supporting circuits comprising a plurality of circuit columns corresponding to the plurality of pixel columns, wherein each of the plurality of circuit columns comprises a plurality of circuit sub-columns corresponding the plurality of pixel sub-columns, and, wherein the plurality of supporting circuits disposed on the one or more additional substrates are each only connected to one of the plurality of pixel sub-columns;

a circuit sub-column bus corresponding to each of the plurality of pixel sub-columns; and

a plurality of interconnects for electrically connecting a pixel sub-column bus with a corresponding circuit sub-column bus;

wherein the plurality of supporting circuits located on the one or more additional substrates that are proximal to the first substrate in each of the circuit sub-columns are configured to independently read and process data from corresponding pixel sub-columns, and wherein pixel sub-columns within a same pixel column are read simultaneously as part of a rolling shutter.

12. The imaging sensor of claim 11 , wherein each pixel sub-column bus is at least partially superimposed relative to a corresponding circuit sub-column bus on the one or more additional substrates, wherein the first substrate and the one or more additional substrates are in a stacked configuration.

13. The imaging sensor of claim 11 , wherein each pixel sub-column is electronically isolated from other pixel sub-columns.

14. The imaging sensor of claim 11 , wherein supporting circuits within a specific circuit sub-column are dedicated to a corresponding to pixel sub-column of the pixel array.

15. The imaging sensor of claim 11 , wherein reading pixel sub-columns within the same pixel column simultaneously comprises:

reading and processing data, by supporting circuits within a specific circuit sub-column, in parallel within supporting circuits located in circuit sub-columns within the same circuit column.

16. An imaging method comprising:

receiving and converting electromagnetic energy to data or data signals using a pixel array on a first substrate, the pixel array comprising a plurality of pixel columns, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns; and

processing the data or data signals by a plurality of supporting circuits, wherein the plurality of supporting circuits are located on one or more additional substrates proximal to the first substrate, the plurality of supporting circuits comprising a plurality of circuit columns corresponding to and each connected only to one pixel column in the plurality of pixel columns, wherein each of the plurality of circuit columns comprises a plurality of circuit sub-columns corresponding the plurality of pixel sub-columns;

wherein the plurality of supporting circuits located on the one or more additional substrates that are proximal to the first substrate in each of the circuit sub-columns independently read and process data from a corresponding pixel sub-column, and wherein pixel sub-columns within a same pixel column are read simultaneously as part of a rolling shutter.

17. The imaging method of claim 16 , wherein reading and processing data from the pixel sub-columns comprises starting with a first pixel in each pixel sub-column within a same pixel column and sequentially reading pixel data from each subsequent pixel in the pixel sub-columns within the same pixel column a last pixel in each pixel sub-column within the pixel column is read.

18. The imaging method of claim 16 , wherein the supporting circuits read the pixel data or signals via interconnects between pixel sub-columns and corresponding circuit sub-columns, wherein the data or signals from one pixel sub-column is processed by one circuit sub-column.

19. The imaging method of claim 16 , further comprising processing the data or data signals into an image.

20. The imaging method of claim 16 , wherein reading pixel sub-columns within the same pixel column simultaneously comprises:

reading and processing data, by supporting circuits within a specific circuit sub-column, in parallel within supporting circuits located in circuit sub-columns within the same circuit column.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: BLANQUART, LAURENT
To: DEPUY SYNTHES PRODUCTS, INC.
Reel/Frame 042134/0676 →
Continuity (6)
Continuation 13471432 · May 14, 2012
Provisional Application 61485432 · May 12, 2011
Provisional Application 61485440 · May 12, 2011
Provisional Application 61485435 · May 12, 2011
Provisional Application 61485426 · May 12, 2011
Related Publication 20170221945A1 · Aug 3, 2017