IP Library Granted Patent US 9,865,644
Granted Patent B2
US 9,865,644 · App. 15/489,794 · Granted Jan 9, 2018

Image sensor

Inventor: Hiroyuki Sekine (Kanagawa, JP)
Assignee: NLT TECHNOLOGIES, LTD.
H01L27/14658H01L27/14612H01L27/14636H01L29/24H01L29/78669H01L29/78693H04N5/378
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Quick Facts
Patent No.
US 9,865,644
App. No.
15/489,794
Granted
Jan 9, 2018
Kind
B2
Abstract

With an image sensor in which the amplifier circuit is disposed at each pixel, there is such an issue that the threshold voltage of the transistor fluctuates so that the signal voltage fluctuates because a voltage is continuously applied between the source and the gate of the transistor at all times when using the amorphous thin film semiconductor as the transistor that constitutes an amplifier circuit. The gate-source potential of the TFT that constitutes the amplifier circuit is controlled so that the gate terminal voltage becomes smaller than the source terminal voltage in an integrating period where the pixels accumulate the signals, and controlled so that the gate terminal voltage becomes larger than the source terminal voltage in a readout period where the pixels output the signals.

Claims (16)

1. An image sensor, comprising:

a photodiode;

a first Thin Film Transistor (TFT);

a second TFT; and

a third TFT, the photodiode, the first TFT, the second TFT, and the third TFT being provided at each pixel, wherein:

an anode terminal of the photodiode is connected to a gate terminal of the first TFT and a source terminal of the third TFT, and a cathode terminal is connected to a first control signal line,

a drain terminal of the first TFT is connected to a first power source line, and a source terminal is connected to a drain terminal of the second TFT,

a gate terminal of the second TFT is connected to the first control signal line, and a source terminal is connected to an output signal line,

a gate terminal of the third TFT is connected to a second control signal line, and a drain terminal is connected to a second power source line, and

a capacitance between the source terminal and the gate terminal of the second TFT is smaller than a capacitance between the source terminal and the gate terminal of the first TFT.

2. The image sensor as claimed in claim 1 , wherein

the first to third TFTs are formed with an amorphous silicon or an oxide semiconductor.

3. The image sensor as claimed in claim 1 , wherein:

a driving period of the image sensor is divided into an integrating period where a light signal is irradiated to the pixels and a readout period where a signal is read out from the pixels;

a gate voltage of the first TFT is set to be smaller than a source voltage of the first TFT in the integrating period; and

the gate voltage of the first TFT is set to be larger than the source voltage of the first TFT in the readout period.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2019
From: TIANMA JAPAN, LTD. (FORMERLY NLT TECHNOLOGIES, LTD.)
To: TIANMA MICROELECTRONICS CO., LTD.
Reel/Frame 050582/0869 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2017
From: SEKINE, HIROYUKI
To: NLT TECHNOLOGIES, LTD.
Reel/Frame 042039/0568 →
Priority Claims (1)
JP 2014-149909 · Jul 23, 2014 · national
Continuity (2)
Division 14806833 · Jul 23, 2015
Related Publication 20170221958A1 · Aug 3, 2017