Spread spectrum clock generator

1. A clock generator comprising:

a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase difference between the reference clock signal and the feedback clock signal;

a voltage-controlled oscillator that oscillates at an oscillating frequency corresponding to the control voltage, and generates an output clock signal;

a waveform generator circuit that receives the feedback clock signal, and generates a waveform signal;

a delta-sigma modulator that receives the waveform signal;

a control circuit that controls a multiplication number according to an output signal of the delta-sigma modulator; and

a divider that generates the feedback clock signal by dividing the output clock signal according to the multiplication number controlled by the control circuit, and supplies the feedback clock signal to the phase comparing unit,

wherein the delta-sigma modulator outputs bits larger than 1 bit based on the waveform signal.

2. The clock generator according to claim 1 , wherein the multiplication number used by the divider to divide the output clock signal takes on an integer value.

3. A clock generator comprising:

a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase difference between the reference clock signal and the feedback clock signal;

a voltage-controlled oscillator that oscillates at an oscillating frequency corresponding to the control voltage, and generates an output clock signal;

a waveform generator circuit that receives the feedback clock signal, and generates a waveform signal;

a delta-sigma modulator that receives the waveform signal;

a control circuit that controls a multiplication number according to an output signal of the delta-sigma modulator;

a divider that generates the feedback clock signal by dividing the output clock signal according to the multiplication number controlled by the control circuit, and supplies the feedback clock signal to the phase comparing unit,

wherein the delta-sigma modulator outputs bits larger than 1 bit based on the waveform signal, and

wherein the multiplication number used by the divider to divide the output clock signal takes on a value which is an integer multiple of 0.5.

4. A clock generator comprising:

a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase difference between the reference clock signal and the feedback clock signal;

a voltage-controlled oscillator that oscillates at an oscillating frequency corresponding to the control voltage, and generates an output clock signal;

a waveform generator circuit that receives the feedback clock signal, and generates a waveform signal;

a delta-sigma modulator that receives the waveform signal;

a control circuit that controls a multiplication number according to an output signal of the delta-sigma modulator; and

a divider that generates the feedback clock signal by dividing the output clock signal according to the multiplication number controlled by the control circuit, and supplies the feedback clock signal to the phase comparing unit,

wherein the delta-sigma modulator outputs bits larger than 1 bit based on the waveform signal,

wherein the delta-sigma modulator includes:

an integrator circuit,

a quantizer that quantizes an integration value of the integrator circuit, and

a decoder that feeds back an output of the quantizer to an input of the delta-sigma modulator,

the integrator circuit integrates a difference signal between the waveform signal and an output signal of the decoder, and

a threshold interval of quantization performed by the quantizer includes a threshold interval less than a quantization interval.

5. A clock generator comprising:

a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase difference between the reference clock signal and the feedback clock signal;

a voltage-controlled oscillator that oscillates at an oscillating frequency corresponding to the control voltage, and generates an output clock signal;

a waveform generator circuit that receives the feedback clock signal, and generates a waveform signal;

a delta-sigma modulator that receives the waveform signal;

a control circuit that controls a multiplication number according to an output signal of the delta-sigma modulator;

a divider that generates the feedback clock signal by dividing the output clock signal according to the multiplication number controlled by the control circuit, and supplies the feedback clock signal to the phase comparing unit, wherein the delta-sigma modulator outputs bits larger than 1 bit based on the waveform signal,

a waveform shaper that receives the waveforms signal, shapes a waveform in a predetermined amplitude range such that an amplitude settles outside the predetermined amplitude range, and supplies the shaped waveform to the delta-sigma modulator.

6. The spread spectrum clock generator according to claim 5 , wherein the waveform shaper changes an amplitude value of the waveform in the predetermined amplitude range to a boundary value outside the predetermined amplitude range.

7. The spread spectrum clock generator according to claim 6 , further comprising a decoder circuit that determines the boundary value based on a frequency of the waveform signal, a degree of modulation for spreading a spectrum of the output clock signal and the multiplication number.

8. The spread spectrum clock generator according to claim 1 , wherein the waveform signal is a triangular wave signal.

9. The spread spectrum clock generator according to claim 1 , wherein the delta-sigma modulator outputs ternary values.