IP Library Granted Patent US 10,026,380
Granted Patent B2
US 10,026,380 · App. 15/491,445 · Granted Jul 17, 2018

Display device

Inventor: Yasuo Saruhashi (Tokyo, JP)
Assignee: Japan Display Inc.
G09G5/10G09G2300/0465G09G2320/0233G09G2330/021
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Quick Facts
Patent No.
US 10,026,380
App. No.
15/491,445
Granted
Jul 17, 2018
Kind
B2
Abstract

A display device include a division circuit dividing an input image from a plurality of pixels into a plurality of regions based on the feature quantity of each of the plurality of pixels, a luminance reduction rate calculation circuit calculating the reduction rate of luminance of each region based on the surface area of each of the plurality of regions, an image generation circuit generating output images by correcting the luminance of each of the plurality of pixels based on the reduction rate calculated by the luminance reduction rate calculation circuit, and a correction circuit correcting labels assigned to each of the plurality of pixels by the division circuit. The division circuit is configured to divide the input image by assigning different labels to each region of the plurality of pixels.

Claims (13)

1. A display device comprising:

a division circuit dividing an input image from a plurality of pixels into a plurality of regions based on feature quantity of each of the plurality of pixels;

a luminance reduction rate calculation circuit calculating the reduction rate of luminance of each region based on the surface area of each of the plurality of regions;

an image generation circuit generating output images by correcting the luminance of each of the plurality of pixels based on the reduction rate calculated by the luminance reduction rate calculation circuit; and

a correction circuit correcting labels assigned to each of the plurality of pixels by the division circuit,

wherein the division circuit is configured to divide the input image by assigning different labels to each region of the plurality of pixels.

2. The display device according to claim 1 , wherein the division circuit determines whether or not feature quantity of a first pixel among the plurality of pixels is the same as feature quantity of a second pixel adjacent to the first pixel, and when the division circuit determines that they are the same, assigns the same label to the first pixel and the second pixel.

3. The display device according to claim 2 , wherein the division circuit determines whether or not the feature quantity of the first pixel and the feature quantity of the second pixel are the same by determining whether or not the feature quantity of the first pixel and the feature quantity of the second pixel are within a range represented by a predetermined value.

4. The display device according to claim 1 , wherein the correction circuit is configured to determine whether or not feature quantity of a third pixel among the plurality of pixels and feature quantity of a first region belonging to the third pixel among a plurality of regions are the same, and assigns a new label to a part including the third pixel inside the first region when it is determining that they are not the same.

5. The display device according to claim 4 , wherein the correction circuit determines whether or not the feature quantity of the third pixel and the feature quantity of the first region are the same by determining whether or not the feature quantity of the third pixel and the feature quantity of the first region are within a range of a predetermined value.

6. The display device according to claim 4 , wherein the correction circuit is configured to determine whether or not feature quantity of a second and a third region adjacent to each other among the plurality of regions are the same, and when it is determined that they are the same, changes the label of the pixel in the third region to the label of the pixel in the second region.

7. The display device according to claim 6 , wherein the correction circuit determines whether or not the feature quantity of the second region and the feature quantity of the third region are the same by determining whether or not the feature quantity of the second region and the feature quantity of the third region are within a range of a predetermined value.

8. The display device according to claim 1 , wherein the luminance reduction rate calculation circuit calculates the surface area of each of the plurality of regions decided by the labels corrected by the division circuit, and calculates the reduction rate of luminance for each of the plurality of regions based on those results.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2017
From: SARUHASHI, YASUO
To: JAPAN DISPLAY INC.
Reel/Frame 042283/0898 →
Priority Claims (1)
JP 2016-087977 · Apr 26, 2016 · national
Continuity (1)
Related Publication 20170309251A1 · Oct 26, 2017