IP Library Patent Application 15494109
Patent Application
App. No. 15/494,109

SECURE DATA STORAGE BASED ON PHYSICALLY UNCLONABLE FUNCTIONS

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Quick Facts
Patent No.
US None
App. No.
15/494,109
Abstract

Technologies are generally described for partial programming of memory having physically unclonable functions for secure data storage. In some examples, a sender that wishes to securely send data to a recipient using a physical memory may measure a program threshold average and a program threshold variation for bits in the memory and group the bits into different bins based on the measured average and variation. The sender may partially program the data to a set of bits selected from one or more of the bins by applying partial program pulses to the bits based on the program threshold average and the program threshold variation. The sender may then provide the partially-programmed memory to the recipient. The recipient may then partially program the received memory based on the program threshold average and the program threshold variation to recover the programmed data.

Claims (61)

1 . A method to read data from a nonvolatile memory using a physically unclonable function, the method comprising:

applying at least one program pulse to at least one bit in a plurality of memory bits in the nonvolatile memory based on at least one of a program threshold average, a program threshold variation, and a bit group characterization associated with the at least one bit;

reading a resulting state of the plurality of memory bits; and

deriving a final data based on the resulting state.

2 . The method of claim 1 , further comprising reading an initial state for the plurality of memory bits, and wherein deriving the final data comprises deriving the final data based on at least the resulting state and the initial state.

3 . The method of claim 2 , further comprising deriving a first program parameter from the program threshold average and the program threshold variation, and wherein applying the at least one program pulse comprises applying a number of program pulses equal to the first program parameter to every bit in the plurality of memory bits.

4 . The method of claim 3 , further comprising:

deriving a second program parameter from the program threshold average and the program threshold variation;

applying a number of program pulses equal to the second program parameter to every bit in the plurality of memory bits; and

reading another state of the plurality of memory bits, wherein deriving the final data comprises deriving the final data based on at least the resulting state, the initial state, and the other state.

5 . The method of claim 1 , further comprising:

grouping, based on the bit group characterization, the plurality of memory bits into a first bit group, a second bit group, and a third bit group; and

deriving, from the program threshold average and the program threshold variation, a first program parameter and a third program parameter, wherein:

applying the at least one program pulse comprises:

applying a number of program pulses equal to the first program parameter to bits in the plurality of memory bits in the second bit group; and

applying a number of program pulses equal to the third program parameter to bits in the plurality of memory bits in the first bit group.

6 . An apparatus, comprising:

a decoder configured to read data from a nonvolatile memory by use of a physically unclonable function;

an interface configured to couple to a plurality of memory bits in the nonvolatile memory; and

a processor coupled to the interface and the decoder, the processor configured to operate with the interface and the decoder to:

apply at least one program pulse to at least one bit in the plurality of memory bits based on at least one of a program threshold average, a program threshold variation, and a bit group characterization associated with the at least one bit, wherein the program threshold represents a number of program pulses to modify a bit in the plurality of memory bits from a first value to a second value;

read a resulting state of the plurality of memory bits; and

derive a final data based on the resulting state.

7 . The apparatus of claim 6 , wherein the processor is configured to:

read an initial state for the plurality of memory bits; and

derive the final data based on at least the resulting state and the initial state.

8 . The apparatus of claim 7 , wherein the processor is configured to:

derive a first program parameter from the program threshold average and the program threshold variation; and

apply the at least one program pulse by application of a number of program pulses equal to the first program parameter to every bit in the plurality of memory bits.

9 . The apparatus of claim 8 , wherein the processor is configured to:

derive a second program parameter from the program threshold average and the program threshold variation;

apply a number of program pulses equal to the second program parameter to every bit in the plurality of memory bits;

read another state of the plurality of memory bits; and

derive the final data based on at least the resulting state, the initial state, and the other state.

10 . The apparatus of claim 6 , wherein the processor is configured to:

group, based on the bit group characterization, the plurality of memory bits into a first bit group, a second bit group, and a third bit group;

derive, from the program threshold average and the program threshold variation, a first program parameter and a third program parameter, and

apply the at least one program pulse by:

application of a number of program pulses equal to the first program parameter to bits in the plurality of memory bits in the second bit group; and

application of a number of program pulses equal to the third program parameter to bits in the plurality of memory bits in the first bit group.

11 . A non-transitory computer-readable storage medium having stored thereon computer-executable instructions that, in response to execution, cause a processor to perform or control performance of operations to:

apply at least one program pulse to at least one bit in a plurality of memory bits in a nonvolatile memory based on at least one of a program threshold average, a program threshold variation, and a bit group characterization associated with the at least one bit, wherein the program threshold represents a number of program pulses to modify a bit in the plurality of memory bits from a first value to a second value;

read a resulting state of the plurality of memory bits; and

derive a final data based on the resulting state.

12 . The non-transitory computer-readable storage medium of claim 11 , wherein the executable instructions, in response to execution, cause the processor to perform or control performance of at least one operation to:

read an initial state for the plurality of memory bits; and

derive the final data based on at least the resulting state and the initial state.

13 . The non-transitory computer-readable storage medium of claim 12 , wherein the executable instructions, in response to execution, cause the processor to perform or control performance of at least one operation to:

derive a first program parameter from the program threshold average and the program threshold variation; and

apply the at least one program pulse by application of a number of program pulses equal to the first program parameter to every bit in the plurality of memory bits.

14 . The non-transitory computer-readable storage medium of claim 13 , wherein the executable instructions, in response to execution, cause the processor to perform or control performance of at least one operation to:

derive a second program parameter from the program threshold average and the program threshold variation;

apply a number of program pulses equal to the second program parameter to every bit in the plurality of memory bits;

read another state of the plurality of memory bits; and

derive the final data based on at least the resulting state, the initial state, and the other state.

15 . The non-transitory computer-readable storage medium of claim 11 , wherein the executable instructions, in response to execution, cause the processor to perform or control performance of at least one operation to:

group, based on the bit group characterization, the plurality of memory bits into a first bit group, a second bit group, and a third bit group;

derive, from the program threshold average and the program threshold variation, a first program parameter and a third program parameter; and

apply the at least one program pulse by:

application of a number of program pulses equal to the first program parameter to bits in the plurality of memory bits in the second bit group; and

application of a number of program pulses equal to the third program parameter to bits in the plurality of memory bits in the first bit group.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED ON JANUARY 29, 2019 AT REEL 048373 FRAME 0217 Recorded Sep 22, 2025
From: CRESTLINE DIRECT FINANCE, L.P., AS COLLATERAL AGENT
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 072936/0464 →
SECURITY INTEREST Recorded Jan 29, 2019
From: EMPIRE TECHNOLOGY DEVELOPMENT LLC
To: CRESTLINE DIRECT FINANCE, L.P.
Reel/Frame 048373/0217 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2017
From: KAN, EDWIN
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 042118/0054 →