Distributive-driving of display panel
An apparatus includes an active region, gate lines, source lines, a gate driver, and a source driver. The active region includes a plurality of subpixels. The subpixels correspond to an array of pixels arranged in M rows and N columns. The number of the subpixels is k times of the number of the pixels. The apparatus includes xM gate lines and (k/x)N source lines, where x is a fraction between 1 and 2, and each of xM and (k/x)N is a positive integer. The gate driver is operatively coupled to the active region via the xM gate lines and configured to scan the plurality of subpixels. The source driver is operatively coupled to the active region via the (k/x)N source lines and configured to write display data in a frame to the plurality of subpixels.
1. An apparatus, comprising:
an active region comprising a plurality of subpixels, wherein the subpixels correspond to an array of pixels arranged in M rows and N columns and are arranged in a plurality of rows of subpixels, and a number of the subpixels is k times of a number of the pixels;
xM gate lines and (k/x)N source lines, wherein x is a fraction between 1 and 2, and each of xM and (k/x)N is a positive integer, wherein each of the xM gate lines are connected to subpixels of different rows of subpixels and a logic connection pattern of subpixels connected by each of the xM gate lines extends along a non-straight direction;
a gate driver operatively coupled to the active region via the xM gate lines and configured to scan the plurality of subpixels; and
a source driver operatively coupled to the active region via the (k/x)N source lines and configured to write display data in a frame to the plurality of subpixels.
2. The apparatus of claim 1 , wherein the display data in the frame comprises M×N pieces of pixel data, each piece of pixel data corresponding to one of the array of pixels and comprising a first component representing a first color, a second component representing a second color, and a third component representing a third color.
3. The apparatus of claim 1 , wherein the apparatus is a display with a resolution of N×M.
4. The apparatus of claim 1 , wherein
x is represented as p/q;
each of p and q is a positive integer; and
p is larger than q and is smaller than 2q.
5. The apparatus of claim 4 , wherein x is 3/2, 4/3, 5/3, 5/4, 7/4, 6/5, 7/5, 8/5, 9/5, 7/6, 11/6, 8/7, 9/7, 10/7, 11/7, 12/7, 13/7, 9/8, 11/8, 13/8, 15/8, 10/9, 11/9, 13/9, 14/9, 16/9, or 17/9.
6. The apparatus of claim 1 , further comprising control logic operatively coupled to the gate driver and source driver, the control logic comprising:
a data interface configured to receive original display data;
a data converting module configured to convert the original display data into converted display data based on the (k/x)N source lines; and
a control signal generating module configured to:
provide a first set of control signals to the gate driver to control the gate driver to scan the plurality of subpixels via the xM gate lines, and
provide a second set of control signals to the source driver to control the source driver to write the converted display data to the plurality of subpixels.
7. The apparatus of claim 6 , wherein the control logic is in a chip-on-film (COF) package.
8. The apparatus of claim 7 , wherein the COF package is a single-layer COF package.
9. The apparatus of claim 1 , wherein
the subpixels display a plurality of different colors;
subpixels of different colors are arranged in different rows of subpixels, adjacent rows of subpixels being staggered with each other; and
each of the xM gate lines is connected to subpixels in at least two adjacent rows of subpixels.
10. The apparatus of claim 1 , wherein adjacent rows of subpixels are staggered with each other and adjacent logic connection patterns are different from each other.
11. An apparatus, comprising:
an active region comprising a plurality of subpixels, wherein the subpixels correspond to an array of pixels arranged in M rows and N columns and are arranged in a plurality of rows of subpixels, and a number of the subpixels is k times of a number of the pixels;
xM gate lines, and (k/x)N source lines, wherein x is a fraction between 0 and 1, and each of xM and (k/x)N is a positive integer, wherein each of the xM gate lines are connected to subpixels of different rows of subpixels and a logic connection pattern of subpixels connected by each of the xM gate lines extends along a non-straight direction;
a gate driver operatively coupled to the active region via the xM gate lines and configured to scan the plurality of subpixels; and
a source driver operatively coupled to the active region via the (k/x)N source lines and configured to write display data in a frame to the plurality of subpixels.
12. The apparatus of claim 11 , wherein the display data in the frame comprises M×N pieces of pixel data, each piece of pixel data corresponding to one of the array of pixels and comprising a first component representing a first color, a second component representing a second color, and a third component representing a third color.
13. The apparatus of claim 11 , wherein the apparatus is a display with a resolution of N×M.
14. The apparatus of claim 11 , wherein
x is represented as p/q;
each of p and q is a positive integer; and
q is larger than p.
15. The apparatus of claim 14 , wherein p equals 1.
16. The apparatus of claim 14 , wherein p is greater than 1.
17. The apparatus of claim 11 , further comprising a demultiplexing module operatively coupled to the (k/x)N source lines and configured to:
receive the display data in kN data channels; and
route the display data to the (k/x)N source lines.
18. The apparatus of claim 17 , wherein the demultiplexing module comprises:
a selecting unit configured to generate kN sets of selecting signals; and
kN demultiplexers, each demultiplexer operatively coupled to the selecting unit and 1/x source lines and configured to receive input display data from one of the kN data channels, and provide output display data to one of the 1/x source lines at each clock period based on the respective set of selecting signals.
19. The apparatus of claim 11 , further comprising control logic operatively coupled to the gate driver and source driver, the control logic comprising:
a data interface configured to receive original display data;
a data converting module configured to convert the original display data into converted display data based on the (k/x)N source lines; and
a control signal generating module configured to:
provide a first set of control signals to the gate driver to control the gate driver to scan the plurality of subpixels via the xM gate lines, and
provide a second set of control signals to the source driver to control the source driver to write the converted display data to the plurality of subpixels.
20. The apparatus of claim 19 , wherein the control logic is in a chip-on-film (COF) package.
21. The apparatus of claim 20 , wherein the COF package is a single-layer COF package.
22. The apparatus of claim 11 , wherein
the subpixels display a plurality of different colors;
subpixels of different colors are arranged in different rows of subpixels, adjacent rows of subpixels being staggered with each other; and
each of the xM gate lines is connected to subpixels in at least two adjacent rows of subpixels.
23. The apparatus of claim 11 , wherein adjacent rows of subpixels are staggered with each other and adjacent logic connection patterns are different from each other.
24. An apparatus, comprising:
an active region comprising a plurality of subpixels, wherein the subpixels correspond to an array of pixels arranged in M rows and N columns and are arranged in a plurality of rows of subpixels, and a number of the subpixels is k times of a number of the pixels;
xM gate lines and (k/x)N source lines, wherein x is a fraction between 0 and 2, and each of xM and (k/x)N is a positive integer, wherein each of the xM gate lines are connected to subpixels of different rows of subpixels and a logic connection pattern of subpixels connected by each of the xM gate lines extends along a non-straight direction;
control logic comprising:
a data interface configured to receive original display data in a frame;
a data converting module configured to convert the original display data into converted display data based on the (k/x)N source lines, and
a control signal generating module configured to generate control signals;
a gate driver operatively coupled to the active region via the xM gate lines and configured to scan the plurality of subpixels based on at least some of the control signals; and
a source driver operatively coupled to the active region via the (k/x)N source lines and configured to write the converted display data to the plurality of subpixels based on at least some of the control signals.
25. An apparatus, comprising:
an active region comprising a plurality of subpixels, wherein the subpixels correspond to an array of pixels arranged in M rows and N columns, and a number of the subpixels is k times of a number of the pixels;
xM gate lines and (k/x)N source lines, wherein x is equal to one of ½, ⅔, ¾, 4/3, 5/3, 5/4, 7/4, 6/5, 7/5, 8/5, 9/5, 7/6, 11/6, 8/7, 9/7, 10/7, 11/7, 12/7, 13/7, 9/8, 11/8, 13/8, 15/8, 10/9, 11/9, 13/9, 14/9, 16/9, or 17/9, and each of xM and (k/x)N is a positive integer;
a gate driver operatively coupled to the active region via the xM gate lines and configured to scan the plurality of subpixels; and
a source driver operatively coupled to the active region via the (k/x)N source lines and configured to write display data in a frame to the plurality of subpixels.
26. The apparatus of claim 25 , wherein
x is equal to ⅔; and
each of the xM gate lines is connected to subpixels arranged at least one row of subpixel and a fraction of another row of subpixel.