Device for protection against electrostatic discharges with a distributed trigger circuit

1. A device for protecting against electrostatic discharges, comprising:

a semiconductor film situated on a buried isolation layer which is situated on top of a semiconductor well;

a first terminal;

a second terminal;

at least one module comprising at least one MOS transistor coupled between the first terminal and the second terminal and having a gate region, a substrate region and the semiconductor well electrically coupled;

at least one resistive-capacitive circuit configured to render the at least one MOS transistor conducting in response to an electrostatic discharge at one of the first terminal and the second terminal;

wherein the at least one resistive-capacitive circuit has a common part with at least one of a source region, the gate region and a drain region of the at least one MOS transistor and comprising a capacitive element and a resistive element, a first electrode of the capacitive element comprising the resistive element and a second electrode of the capacitive element comprising at least a portion of the semiconductor film.

2. The device according to claim 1 , wherein the gate region comprises a first polysilicon region and the at least one module comprises a first dummy gate region situated on top of the drain region of the at least one MOS transistor and comprising a second polysilicon region formed on top of a first insulating layer, the second polysilicon region being electrically coupled to the first polysilicon region and comprising a first portion without any metal silicide, the at least one module further comprising a first resistive-capacitive circuit comprising a resistive element comprising the first portion of the second polysilicon region and a capacitive element having a first electrode comprising the second polysilicon region and a second electrode comprising a portion of the drain region situated under the first insulating layer.

3. The device according to claim 1 , wherein the gate region comprises a first polysilicon region, situated on top of an insulating layer and comprising a portion without any metal silicide, and the at least one module comprises a second resistive-capacitive circuit comprising a resistive element comprising the portion of the first polysilicon region and a capacitive element having a first electrode comprising the first polysilicon region and a second electrode comprising a portion of the substrate region situated under the insulating layer.

4. The device according to claim 1 , wherein the gate region comprises a first polysilicon region and the at least one module comprises a second dummy gate region situated on top of the source region and comprising a third polysilicon region situated on a third insulating layer, the third polysilicon region being electrically coupled to the first polysilicon region and comprising a portion without any metal silicide, the module comprising a third resistive-capacitive circuit comprising a resistive element comprising the portion of the third polysilicon region and a capacitive element having a first electrode comprising the third polysilicon region and a second electrode comprising a portion of the source region situated facing the third insulating layer.

5. The device according to claim 1 , wherein the semiconductor well comprises a region less heavily doped than a layer situated under the buried isolation layer, and the at least one module comprises a fourth resistive-capacitive circuit electrically coupled to the substrate region of the transistor, said fourth resistive-capacitive circuit having a resistive element comprising a less heavily doped region of the semiconductor well and a capacitor having a first electrode comprising the less heavily doped region of the semiconductor well and a second electrode comprising the semiconductor film situated on top of the buried isolation layer.

6. The device according to claim 1 , wherein said at least one module comprises a plurality of modules coupled in parallel between the first terminal and the second terminal.

7. The device according to claim 6 , wherein the resistive-capacitive circuits of said plurality of modules are electrically coupled.

8. An integrated circuit, comprising:

a semiconductor film situated on a buried isolation layer which is situated on top of a semiconductor well;

a first terminal;

a second terminal;

a circuit component coupled between said first and second terminals; and

a module configured to protect said circuit component against electrostatic discharge, said module comprising:

at least one MOS transistor coupled between the first terminal and the second terminal and having a gate region, a substrate region and the semiconductor well electrically coupled;

at least one resistive-capacitive circuit configured to render the at least one MOS transistor conducting in response to an electrostatic discharge at one of the first terminal and the second terminal;

wherein the at least one resistive-capacitive circuit has a common part with at least one of a source region, the gate region and a drain region of the at least one MOS transistor and comprising a capacitive element and a resistive element, a first electrode of the capacitive element comprising the resistive element and a second electrode of the capacitive element comprising at least a portion of the semiconductor film.

9. A device for protecting against electrostatic discharges, comprising:

a semiconductor film situated on a buried isolation layer which is situated on top of a semiconductor well;

a source region, a body region and a drain region each formed by a portion of said semiconductor film;

a first terminal electrically connected to the source region;

a second terminal electrically connected to the drain region;

an insulated transistor gate extending over said body region;

an insulated dummy gate extending over said drain region between the second terminal and the insulated transistor gate, said insulated dummy gate having a first electrical connection to the insulated transistor gate and a second electrical connection to the semiconductor well;

wherein the insulated dummy gate forms a resistive element extending between the first and second electrical connections; and

wherein a capacitive element includes a first electrode formed by said insulated dummy gate and a second electrode formed by said drain region.

10. The device of claim 9 , wherein the semiconductor well includes a more heavily doped region adjacent to the buried isolation layer.

11. The device of claim 9 , wherein the first terminal is formed by a first silicide region in contact with the source region, and wherein the second terminal is formed by a second silicide region in contact with the drain region.

12. The device of claim 11 , wherein the insulated dummy gate extends over said drain region at a location where the second silicide region is not present.

13. A device for protecting against electrostatic discharges, comprising:

a semiconductor film situated on a buried isolation layer which is situated on top of a semiconductor well;

a source region, a body region and a drain region each formed by a portion of said semiconductor film;

a first terminal electrically connected to the source region;

a second terminal electrically connected to the drain region;

an insulated transistor gate extending over said body region;

an insulated dummy gate extending over said source region between the first terminal and the insulated transistor gate, said insulated dummy gate having a first electrical connection to the insulated transistor gate and a second electrical connection to the semiconductor well;

wherein the insulated dummy gate forms a resistive element extending between the first and second electrical connections; and

wherein a capacitive element includes a first electrode formed by said insulated dummy gate and a second electrode formed by said source region.

14. The device of claim 13 , wherein the semiconductor well includes a more heavily doped region adjacent to the buried isolation layer.

15. The device of claim 13 , wherein the first terminal is formed by a first silicide region in contact with the source region, and wherein the second terminal is formed by a second silicide region in contact with the drain region.

16. The device of claim 15 , wherein the insulated dummy gate extends over said source region at a location where the first silicide region is not present.