IP Library Granted Patent US 10,372,345
Granted Patent B1
US 10,372,345 · App. 15/499,276 · Granted Aug 6, 2019

High performance logical device

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Quick Facts
Patent No.
US 10,372,345
App. No.
15/499,276
Granted
Aug 6, 2019
Kind
B1
Abstract

A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.

Claims (38)

1. A method of processing an I/O operation comprising:

receiving, on a host, the I/O operation directed to a target location of a logical device having storage provisioned on a data storage system;

determining, by the host, a director of the data storage system, wherein the director is designated as a primary director for the logical device and wherein the primary director locally accesses a first cache location of the cache of the data storage system, wherein the first cache location is used to store cache data for the target location of the logical device; and

sending the I/O operation from the host to the data storage system over a path, said path being a connection from the host to the director of the data storage system, wherein the I/O operation writes first data to the logical device and wherein the director stores the first data in the first cache location of a first global memory portion of a plurality of global memory portions, and wherein host-based processing is performed to mirror the first data of the first cache location in another cache location that includes the host performing first processing comprising:

determining whether the I/O operation is a write operation and whether the logical device, to which the I/O operation is directed, is designated as a high performance logical device; and

responsive to determining the I/O operation is a write operation and the logical device, to which the I/O operation is directed, is designated as a high performance logical device, performing additional processing including sending a second write operation that also writes the first data in the another cache location of another one of the plurality of global memory portions.

2. The method of claim 1 , wherein the target location denotes a logical address or location on the logical device.

3. The method of claim 1 , wherein the primary director is a specified one of a plurality of directors of the data storage system that exclusively processes I/O operations directed to the logical device.

4. The method of claim 3 , wherein the first cache location is included in the first global memory portion that is local with respect to the director.

5. The method of claim 4 , wherein the data storage system includes a distributed global memory comprising the plurality of global memory portions including the first global memory portion, each of the plurality of directors locally accessing a different one of the plurality of global memory portions, and wherein the cache of the data storage system comprises groups of multiple cache locations, each of the groups of multiple cache locations being included in a different one of the global memory portions.

6. The method of claim 5 , wherein the logical device is configured as a high performance logical device.

7. The method of claim 6 , wherein the primary director is the only one of the plurality of directors that accesses memory chunks of the first global memory portion and controls used in connection with shared or concurrent access to the memory chunks are disabled.

8. The method of claim 6 , wherein the data storage system include a plurality of engines including the first engine, and a second logical device is not configured as a high performance logical device, wherein the data storage system automatically performs second processing to mirror second cached write data of the second logical device on two different cache locations of two different engines of the plurality of engines, the second processing including copying the second cached write data over a communications fabric connected to each of the plurality of directors and each of the plurality of global memory portions of the distributed global memory.

9. The method of claim 6 , wherein the primary director is included in a first engine and a second director is also included in the first engine, wherein the plurality of global memory portions of the distributed global memory includes a second global memory portion that is local with respect to the second director, and wherein the host-based processing is performed to mirror first cached write data of the logical device in the first global memory portion and the second global memory portion.

10. The method of claim 9 , wherein the first cached write data includes the first data written to the logical device by the I/O operation.

11. The method of claim 10 , wherein the second write operation is sent to the second director that stores the first data in the another cache location of the second global memory portion local to the second director.

12. The method of claim 1 , wherein the data storage system includes a plurality of directors on a plurality of engines, each of the plurality of engines including at least two of the plurality of directors, wherein a first of the engines includes the director and a second director, and wherein each of the plurality of directors is configured to communicate over a fabric to access a distributed global memory of a plurality of global memory portions, each of the plurality of global memory portions being local to a different one of the plurality of directors.

13. The method of claim 12 , wherein each of the plurality of engines includes an engine-local connection used for communication between any of the plurality of directors on said each engine, wherein the first global memory portion is local to the director and a second of the plurality of global memory portions is local to the second director, and wherein a second logical device is configured as a high performance logical device, the data storage system automatically mirroring cached write data of the second logical device in the first global memory portion and the second global memory portion, said mirroring including transferring the cached write data of the second logical device, as stored in the first global memory portion, over the engine-local connection of the first engine, to the second global memory portion.

14. A system comprising:

a processor; and

a memory including code stored therein that, when executed by the processor, performs a method of processing an I/O operation comprising:

receiving, on a host, the I/O operation directed to a target location of a logical device having storage provisioned on a data storage system;

determining, by the host, a director of the data storage system, wherein the director is designated as a primary director for the logical device and wherein the primary director locally accesses a first cache location of the cache of the data storage system, wherein the first cache location is used to store cache data for the target location of the logical device; and

sending the I/O operation from the host to the data storage system over a path, said path being a connection from the host to the director of the data storage system, wherein the I/O operation writes first data to the logical device and wherein the director stores the first data in the first cache location of a first global memory portion of a plurality of global memory portions, and wherein host-based processing is performed to mirror the first data of the first cache location in another cache location that includes the host performing first processing comprising:

determining whether the I/O operation is a write operation and whether the logical device, to which the I/O operation is directed, is designated as a high performance logical device; and

responsive to determining the I/O operation is a write operation and the logical device, to which the I/O operation is directed, is designated as a high performance logical device, performing additional processing including sending a second write operation that also writes the first data in the another cache location of another one of the plurality of global memory portions.

15. A non-transitory computer readable medium comprising code stored thereon, that, when executed, performs a method of processing an I/O operation comprising:

receiving, on a host, the I/O operation directed to a target location of a logical device having storage provisioned on a data storage system;

determining, by the host, a director of the data storage system, wherein the director is designated as a primary director for the logical device and wherein the primary director locally accesses a first cache location of the cache of the data storage system, wherein the first cache location is used to store cache data for the target location of the logical device; and

sending the I/O operation from the host to the data storage system over a path, said path being a connection from the host to the director of the data storage system, wherein the I/O operation writes first data to the logical device and wherein the director stores the first data in the first cache location of a first global memory portion of a plurality of global memory portions, and wherein host-based processing is performed to mirror the first data of the first cache location in another cache location that includes the host performing first processing comprising:

determining whether the I/O operation is a write operation and whether the logical device, to which the I/O operation is directed, is designated as a high performance logical device; and

responsive to determining the I/O operation is a write operation and the logical device, to which the I/O operation is directed, is designated as a high performance logical device, performing additional processing including sending a second write operation that also writes the first data in the another cache location of another one of the plurality of global memory portions.

16. The non-transitory computer readable medium of claim 15 , wherein the logical device is configured as a high performance logical device.

17. The non-transitory computer readable medium of claim 16 , wherein the first global portion is memory that is locally accessible to the primary director, wherein the second write operation is sent to a second director of the data storage system, wherein the first director and the second director are included in the same engine, a second global memory portion of the plurality of global memory portions is locally accessible to the second director, and the another cache location is included in the second global memory portion.

18. The non-transitory computer readable medium of claim 17 , wherein cached write data for a second logical device is stored in the first global portion and other processing is performed to mirror the cached write data for the logical device, wherein the other processing includes any of:

performing automated processing by the data storage system to mirror the cached write data for the second logical device in the second global memory portion of the distributed global memory, wherein the cached write data is copied to the second global memory portion over a first engine-local connection between the primary director and the second director; and

performing host-based mirroring in which the host performs processing to mirror the cached write data for the second logical device.

19. The computer readable medium of claim 18 , wherein automated processing is performed by the data storage system to mirror the cached write data for the second logical device in the second global memory portion, and, upon failure of the primary director, the host sends subsequent I/Os that are directed to the second logical device over one or more other paths to the second director, and wherein second processing is performed to mirror cached write data of the subsequent I/Os, said second processing including performing host-based mirroring, or reconfiguring the logical device as a regular logical device whereby cached write data is mirrored in cache locations of one or more global memory portions across multiple engines.

Assignments (11)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (042769/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0802 →
RELEASE OF SECURITY INTEREST AT REEL 042768 FRAME 0585 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058297/0536 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY INTEREST (NOTES) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 042769/0001 →
PATENT SECURITY INTEREST (CREDIT) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 042768/0585 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2017
From: LECRONE, DOUGLAS E.
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 042379/0619 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2017
From: SCHARLAND, MICHAEL J.
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 042301/0016 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2017
From: CARTMELL, JEROME
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 042204/0210 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2017
From: MCCLURE, STEVEN T.
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 042166/0097 →