IP Library Granted Patent US 10,545,809
Granted Patent B2
US 10,545,809 · App. 15/499,369 · Granted Jan 28, 2020

Detection and storage of errors of an information handling system utilizing an embeded controller

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Quick Facts
Patent No.
US 10,545,809
App. No.
15/499,369
Granted
Jan 28, 2020
Kind
B2
Abstract

In one or more embodiments, an embedded controller of the information handling system may detect an error associated with an information handling system before an operating system, executable via a processor of the information handling system, is operable to provide information associated with the error. The embedded controller may store the information associated with the error via a memory medium. The embedded controller may receive a query from operating system executing via the processor. The embedded controller may provide the information associated with the error to the operating system. In one or more embodiments, the embedded controller may detect another error after the operating system is executing and may provide providing information associated with the other error to the operating system upon detection of the other error.

Claims (56)

1. An information handling system, comprising:

a processor;

a first memory medium, coupled to the processor, that stores instructions, which include an operating system, executable by the processor;

an input/output (I/O) port in communication with the processor; and

an embedded controller coupled to the processor;

wherein the embedded controller:

detects an error associated with a first power source coupled to the I/O port of the information handling system before the operating system is operable to provide information associated with the error;

stores the information associated with the error via a second memory medium;

provides the information associated with the error to the operating system when the operating system is operable to provide the information associated with the error,

determines that a second power source is coupled to the I/O port after detecting the error associated with the first power source coupled to the I/O port; and

in response to determining that the second power source is coupled to the I/O port after detecting the error associated with the first power source coupled to the I/O port, removes the error from the second memory medium.

2. The information handling system of claim 1 ,

wherein the embedded controller receives a query from the operating system that executes via the processor; and

wherein the embedded controller provides the information associated with the error to the operating system in response to receiving the query from the operating system.

3. The information handling system of claim 1 ,

wherein the operating system utilizes a management information exchange that permits communications between the operating system and the embedded controller; and

wherein the management information exchange includes at least one of a Windows Management Interface (WMI) and a Common Information Model (CIM).

4. The information handling system of claim 1 ,

wherein the embedded controller detects another error after the operating system is executing via the processor; and

wherein the embedded controller provides information associated with the other error to the operating system upon detection of the other error.

5. The information handling system of claim 1 ,

wherein the operating system, executing via the processor, queries a management information exchange; and

wherein the operating system, executing via the processor, receives the information associated with the error via the management information exchange.

6. The information handling system of claim 1 ,

wherein the operating system, executing via the processor, determines that a user is logged in;

wherein after the operating system determines that the user is logged in, the operating system queries the embedded controller for information associated with at least one of the error, a power-on self-test (POST) event, and a boot sequence.

7. The information handling system of claim 6 , wherein the POST event includes the error.

8. The information handling system of claim 1 ,

wherein the embedded controller determines that the error is at least one of resolved and no longer an issue; and

wherein the embedded controller removes the error from the second memory medium in response to determining that the error is at least one of resolved and no longer the issue.

9. The information handling system of claim 1 , wherein when the embedded controller stores the information associated with the error via the second memory medium, the embedded controller stores the information associated with the error via a data structure.

10. The information handling system of claim 1 , wherein the second memory medium is the first memory medium.

11. A method of operating an information handling system, comprising:

an embedded controller of the information handling system detecting an error associated with a first power source coupled to an input/output (I/O) port in communication with a processor of the information handling system before an operating system, executable via the processor of the information handling system, is operable to provide information associated with the error;

the embedded controller storing the information associated with the error via a memory medium;

the embedded controller providing the information associated with the error to the operating system when the operating system is operable to provide the information associated with the error,

the embedded controller determining that a second power source is coupled to the I/O port after detecting the error associated with the first power source coupled to the I/O port; and

the embedded controller, in response to determining that the second power source is coupled to the I/O port after detecting the error associated with the first power source coupled to the I/O port, removing the error from the memory medium.

12. The method of claim 11 , further comprising:

the embedded controller receiving a query from operating system executing via the processor.

13. The method of claim 11 ,

wherein the operating system utilizes a management information exchange, executing via the processor, that permits communications between the operating system and the embedded controller; and

wherein the management information exchange includes at least one of a Windows Management Interface (WMI) and a Common Information Model (CIM).

14. The method of claim 11 , further comprising:

the embedded controller detecting another error after the operating system is executing; and

the embedded controller providing information associated with the other error to the operating system upon detection of the other error.

15. The method of claim 14 , further comprising:

determining that the user is logged in;

after the determining that a user is logged in, the operating system, executing via the processor, querying the embedded controller for information associated with at least one of the error, a power-on self-test (POST) event, and a boot sequence.

16. The method of claim 15 , wherein the POST event includes the error.

17. The method of claim 11 , further comprising:

the operating system, executing via the processor, querying a management information exchange executing via the processor; and

the operating system, executing via the processor, receiving the information associated with the error via the management information exchange executing via the processor.

18. The method of claim 11 , further comprising:

determining that the error is at least one of resolved and no longer an issue; and

in response to the determining that the error is at least one of resolved and no longer the issue, removing the error from the memory medium.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (042769/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0802 →
RELEASE OF SECURITY INTEREST AT REEL 042768 FRAME 0585 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058297/0536 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY INTEREST (CREDIT) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 042768/0585 →
PATENT SECURITY INTEREST (NOTES) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 042769/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2017
From: KONDAPI, SRIKANTH; MARTELL, NATHAN FRANCIS; CASTRUITA, SEAN-MARC PAUL
To: DELL PRODUCTS L.P.
Reel/Frame 042167/0567 →