Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating
A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
1. A semiconductor memory array comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a bipolar device configured to store data when power is applied to said memory cell; and
a nonvolatile memory comprising a bipolar resistive change element configured to store data stored in said bipolar device upon transfer thereto;
wherein said data stored in said bipolar device determines the resistivity of said bipolar resistive change element upon transfer thereto; and
wherein said transfer is performed to said at least two of said memory cells in parallel.
2. The semiconductor memory array of claim 1 , wherein said resistance change element comprises a material selected from at least one of: transition metal oxide materials, ferroelectric materials and ferromagnetic materials.
3. The semiconductor memory array of claim 1 , wherein said bipolar resistive change element is electrically connected to said bipolar device and a distance between said bipolar resistive change element and said bipolar device, when electrically connected, is in the range from about 90 nm to 1 μm.
4. The semiconductor memory array of claim 1 , further comprising an addressable line electrically connected to said bipolar resistive change element.
5. The semiconductor memory array of claim 4 , wherein said bipolar resistive change element further comprises a conductive material element interconnecting said addressable line and said bipolar resistive change material.
6. The semiconductor memory array of claim 1 , wherein said bipolar device comprises a floating base region.
7. The semiconductor memory array of claim 6 , wherein said floating base region has a first conductivity type selected from n-type conductivity type and p-type conductivity type.
8. The semiconductor memory array of claim 6 , wherein charge stored in said floating base region represents said data stored in said bipolar device.
9. The semiconductor memory array of claim 1 , wherein said bipolar device has a three-dimensional structure comprising a fin structure extending substantially perpendicular to, and above a top surface of a substrate.
10. An integrated circuit comprising:
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include:
a bipolar device configured to store data when power is applied to said memory cell; and
a nonvolatile memory comprising a bipolar resistive change element configured to store data stored in said bipolar device upon transfer thereto;
wherein said data stored in said bipolar device determines the resistivity of said bipolar resistive change element upon transfer thereto;
wherein said transfer is performed to said at least two of said memory cells in parallel; and
a circuitry to perform said transfer.
11. The integrated circuit of claim 10 , wherein said resistance change element comprises a material selected from at least one of: transition metal oxide materials, ferroelectric materials and ferromagnetic materials.
12. The integrated circuit of claim 10 , wherein said bipolar resistive change element is electrically connected to said bipolar device and a distance between said bipolar resistive change element and said bipolar device, when electrically connected, is in the range of from about 90 nm to 1 μm.
13. The integrated circuit of claim 10 , further comprising an addressable line electrically connected to said bipolar resistive change element.
14. The integrated circuit of claim 10 , wherein said bipolar resistive change element further comprises a conductive material element interconnecting said addressable line and said bipolar resistive change material.
15. The integrated circuit of claim 10 , wherein said bipolar device comprises a floating base region.
16. The integrated circuit of claim 15 , wherein said floating base region has a first conductivity type selected from n-type conductivity type and p-type conductivity type.
17. The integrated circuit of claim 15 , wherein charge stored in said floating base region represents said data stored in said bipolar device.
18. The integrated circuit of claim 10 , wherein said bipolar device has a three-dimensional structure comprising a fin structure extending substantially perpendicular to, and above a top surface of a substrate.