Storage device
According to one embodiment, there is provided a storage device including a control chip and a plurality of memory chips. The control chip has an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal. A first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips. In a first mode, the control chip enables the input buffer so as to activate the first transmission path and, in a second mode, disables the input buffer so as to activate the second transmission path.
1. A storage device comprising:
a control chip; and
a plurality of memory chips;
wherein the control chip includes an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal,
a first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips, and
in a first mode, the control chip enables the input buffer to activate the first transmission path and, in a second mode, disables the input buffer to activate the second transmission path,
the control chip includes a first control circuit that, in the first mode, enables the input buffer and that, in the second mode, disables the input buffer,
the control chip further includes a first transfer switch provided on the second transmission path and electrically connected to the external terminal,
in the first mode, the first control circuit maintains the first transfer switch in an off state and, in the second mode, turns on the first transfer switch, and
each of the plurality of memory chips includes:
a second transfer switch provided on the second transmission path and electrically connected to the external terminal; and
a second control circuit that, in the first mode, maintains the second transfer switch in the off state and, in the second mode, turns on the second transfer switch.
2. A storage device comprising:
a control chip; and
a plurality of memory chips;
wherein the control chip includes an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal,
a first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips, and
in a first mode, the control chip enables the input buffer to activate the first transmission path and, in a second mode, disables the input buffer to activate the second transmission path,
the control chip includes a first control circuit that, in the first mode, enables the input buffer and that, in the second mode, disables the input buffer,
the control chip further includes a first transfer switch provided on the second transmission path and electrically connected to the external terminal,
in the first mode, the first control circuit maintains the first transfer switch in an off state and, in the second mode, turns on the first transfer switch, and
each of the plurality of memory chips includes:
a second transfer switch provided on the second transmission path;
a connection switch provided on the second transmission path and that electrically connects the external terminal to the second transfer switch; and
a second control circuit that, in the first mode, maintains at least the connection switch in the off state and, in the second mode, turns on the connection switch and the second transfer switch.
3. A storage device comprising:
a control chip; and
a plurality of memory chips;
wherein the control chip includes an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal,
a first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips, and
in a first mode, the control chip enables the input buffer to activate the first transmission path and, in a second mode, disables the input buffer to activate the second transmission path,
the control chip includes a first control circuit that, in the first mode, enables the input buffer and that, in the second mode, disables the input buffer,
the control chip further includes a first transfer switch provided on the second transmission path,
in the first mode, the first control circuit maintains the first transfer switch in an off state and, in the second mode, turns on the first transfer switch, and
each of the plurality of memory chips includes:
a second transfer switch provided on the second transmission path;
a connection switch provided on the second transmission path and that electrically connects the external terminal to each of the first transfer switch and the second transfer switch; and
a second control circuit that, in the first mode, maintains at least the connection switch in the off state and, in the second mode, turns on each of the connection switch and the second transfer switch.
4. The storage device according to claim 1 , wherein
the first mode includes an operation mode in which a control signal is supplied from the external terminal to a control circuit in each of the control chip and the plurality of memory chips using the first transmission path, and
the second mode includes a test mode in which the operation of each of the control chip and the plurality of memory chips is checked using the second transmission path.
5. The storage device according to claim 2 , wherein
the first mode includes an operation mode in which a control signal is supplied from the external terminal to a control circuit in each of the control chip and the plurality of memory chips using the first transmission path, and
the second mode includes a test mode in which the operation of each of the control chip and the plurality of memory chips is checked using the second transmission path.
6. The storage device according to claim 3 , wherein
the first mode includes an operation mode in which a control signal is supplied from the external terminal to a control circuit in each of the control chip and the plurality of memory chips using the first transmission path, and
the second mode includes a test mode in which the operation of each of the control chip and the plurality of memory chips is checked using the second transmission path.