Semiconductor device
According to one embodiment, M (M represents an integer of 2 or larger) semiconductor chips and through electrodes for N (N represents an integer of 2 or larger) channels are provided. The M semiconductor chips are stacked in sequence. The through electrodes are embedded in the semiconductor chips to connect electrically the semiconductor chips in the direction of stacking. The connection destination of the through electrodes are exchanged between one or more upper and lower layers of the semiconductor chips.
1. A semiconductor device comprising:
M (M represents an integer of 2 or larger) semiconductor chips that are stacked; and
a controller chip that controls the semiconductor chips, wherein
the M semiconductor chips include a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip is stacked on the controller chip and includes
a 1 st through electrode,
a 2 nd through electrode,
a 3 rd through electrode, and
a 4 th through electrode,
the second semiconductor chip is stacked on the first semiconductor chip and includes
a 5 th through electrode,
a 6 th through electrode,
a 7 th through electrode, and
an 8 th through electrode,
the 5 th through electrode is disposed on a location not corresponding to the 4 th through electrode and is electrically connected to the 4 th through electrode,
the 6 th through electrode is disposed on a location not corresponding to the 1 st through electrode and is electrically connected to the 1 st through electrode, and
the 5 th through electrode is disposed on a location corresponding to the 1 st through electrode,
the 6 th through electrode is disposed on a location corresponding to the 2 nd through electrode and is electrically connected to the 1 st through electrode,
the 7 th through electrode is disposed on a location corresponding to the 3 rd through electrode and is electrically connected to the 2 nd through electrode,
the 8 th through electrode is disposed on a location corresponding to the 4 th through electrode and is electrically connected to the 3 rd through electrode,
the controller chip controls a number of channels achieved by the 1 st to 8 th through electrodes by inputting a same signal into two or more through electrodes among the 1 st to 4 th through electrodes or by inputting different signals into the 1 st to 4 th through electrodes,
the controller chip includes
a 1 st transistor whose source is electrically coupled to a 1 st input node and whose drain is electrically coupled to the 1 st through electrode,
a 2 nd transistor whose source is electrically coupled to a 2 nd input node and whose drain is electrically coupled to the 2 nd through electrode,
a 3 rd transistor whose source is electrically coupled to a 3 rd input node and whose drain is electrically coupled to the 3 rd through electrode,
a 4 th transistor whose source is electrically coupled to a 4 th input node and whose drain is electrically coupled to the 4 th through electrode,
a 5 th transistor whose source is electrically coupled to the 4 th input node and whose drain is electrically coupled to the Pt through electrode,
a 6 th transistor whose source is electrically coupled to the 2 nd input node and whose drain is electrically coupled to the 4 th through electrode, and
a 7 th transistor whose source is electrically coupled to the 2 nd input node and whose drain is electrically coupled to the 1 st through electrode.
2. The semiconductor device according to claim 1 , wherein, in order to operate the first and second semiconductor chips with K (K represents an integer of equal to or smaller than M) channels, the controller chip divides the 1 st to 8 th through electrodes into K groups, inputs the same signal into a same group, and inputs the different signals into different groups.
3. The semiconductor device according to claim 1 , wherein the controller chip controls a number of pieces of signals to be input from the 1 st to 4 th input nodes to the 1 st to 4 th through electrodes by controlling on-off states of the 1 st to 7 th transistors.
4. The semiconductor device according to claim 1 , wherein the semiconductor chips are NAND memories.
5. The semiconductor device according to claim 1 , wherein
the first semiconductor chip further includes:
a first internal circuit and
a first interface that electrically connects the 4 th through electrode to the first internal circuit, and
the second semiconductor chip further includes:
a second internal circuit and
a second interface that electrically connects the 4 th through electrode to the second internal circuit.
6. The semiconductor device according to claim 5 , wherein,
the channels include a first channel, a second channel, a third channel, and a fourth channel,
the 1 st through electrode and the 6 th through electrode correspond to the first channel,
second 4 th through electrode and the 5 th through electrode correspond to the second channel,
the 2 nd through electrode and the 7 th through electrode correspond to the third channel,
the 3 rd through electrode and the 8 th through electrode correspond to the fourth channel,
in the first semiconductor chip, the first interface forms the second channel for the first semiconductor chip, and
in the second semiconductor chip, the second interface forms the fourth channel for the second semiconductor chip.
7. The semiconductor device according to claim 6 , wherein
the first interface includes a first AND circuit that takes in a first signal for the second channel according to a first internal enable signal,
the second interface includes a second AND circuit that takes in a second signal for the fourth channel according to a second internal enable signal.
8. The semiconductor device according to claim 7 , wherein
the first semiconductor chip further includes a first logic circuit that generates the first internal enable signal based on a chip address and first chip identification information, and
the second semiconductor chip further includes a second logic circuit that generates the second internal enable signal based on another chip address and second chip identification information.
9. The semiconductor device according to claim 1 , wherein
the 1 st first through electrode, the 4 th through electrode, the 2 nd through electrode, and the 3 rd through electrode are disposed in square form, and
the 5 th through electrode, the 6 th through electrode, the 7 th through electrode, and the 8 th through electrode are disposed in square form.
10. The semiconductor device according to claim 3 , wherein
the signals to be input to the 1 st to 4 th through electrodes include at least one of an address latch enable signal, a command latch enable signal, a read enable signal, a write enable signal, a data signal, a data strobe signal, a chip enable signal, a write protect signal, a ready/busy signals, and a chip address signal.
11. The semiconductor device according to claim 10 , wherein
the controller chip assigns a common signal as the signals to be input to the 1 st to 4 th through electrodes.
12. The semiconductor device according to claim 10 , wherein
the controller chip assigns a first common signal to be input to the 1 st and 4 th through electrodes and assigns a second common signal to be input to the 2 nd and 3 rd through electrodes.
13. The semiconductor device according to claim 10 , wherein
the controller chip assigns a first common signal to be input to the 1 st , 2 nd and 4 th through electrodes and assigns a second signal to be input to the 3 rd through electrode.
14. The semiconductor device according to claim 10 , wherein
the controller chip assigns the different signals as the signals to be input to the 1 st to 4 th through electrodes.
15. The semiconductor device according to claim 10 , wherein
the first semiconductor chip further includes
a first logic circuit that generates a first internal enable signal based on a chip address and first chip identification information, and
the second semiconductor chip further includes
a second logic circuit that generates a second internal enable signal based on another chip address and second chip identification information.
16. The semiconductor device according to claim 15 , wherein
the first semiconductor chip further includes
a first I/O controller that receives the generated first internal enable signal and
a first logic controller that receives the generated first internal enable signal,
the second semiconductor chip further includes
a second I/O controller that receives the generated second internal enable signal and
a second logic controller that receives the generated second internal enable signal.
17. The semiconductor device according to claim 15 , wherein
the first logic circuit activates the first internal enable signal when the chip address matches the first chip identification information, and
the second logic circuit activates the second internal enable signal when the other chip address matches the second chip identification information.