PENETRATION DETECTION BOUNDARY HAVING A HEAT SINK

1 . An apparatus comprising:

a substrate; and

an integrated circuit mounted to the substrate,

wherein:

the substrate comprises a penetration detection boundary to detect a penetration attack and a heat sink to dissipate thermal energy for the integrated circuit;

the boundary comprises a plurality of metal layers associated with the substrate, and the boundary comprising ground traces and penetration detection traces; and

the ground traces are coupled together to form the heat sink.

2 . The apparatus of claim 1 , wherein the integrated circuit comprises a microprocessor core.

3 . The apparatus of claim 1 , wherein the plurality of metal layers comprise a first metal layer, a second metal layer and a third metal layer, the apparatus further comprising:

a first set of vias to extend between the first and second metal layers to electrically couple together ground traces associated with the first and second metal layers; and

a second set of via offset from the first set of vias to extend between the second and third metal layers and electrically couple together the second and third ground traces together.

4 . The apparatus of claim 3 , further comprising:

another metal layer associated with the substrate to form a ground plane,

wherein one of the first and second set of vias extend to the ground plane.

5 . The apparatus of claim 1 , wherein for at least one of the metal layers, at least one ground trace of the plurality of ground traces is embedded in a penetration detection trace of the plurality of penetration detection traces.

6 . The apparatus of claim 1 ,

the plurality of metal layers comprise a first metal layer and a second metal layer;

the ground trace associated with the first metal layer is arranged in a pattern, and the pattern having a first orientation; and

the ground trace associated with the second metal layer is arranged in the pattern, and the pattern having a second orientation different from the first orientation.

7 . A method comprising:

inhibiting a penetration attack targeting at least one integrated circuit mounted on a substrate, wherein inhibiting the penetration attack comprises providing a plurality of layers in the substrate to form a penetration detection boundary;

providing ground traces within the penetration detection boundary; and

coupling the ground traces together to form a heat sink to dissipate thermal energy produced by at least one integrated circuit mounted on the substrate.

8 . The method of claim 7 , further comprising:

coupling the ground traces together using vias; and

routing the ground traces and vias such that a penetration attack along a pathway extending through a given via also extends through at least one of the penetration detection layers.

9 . The method of claim 7 , wherein:

the ground traces comprise sets of ground traces, the ground traces of each set being parallel to each other and being embedded in a different layer of the layers of the penetration detection boundary; and

providing the ground traces comprises routing a given ground trace of at least one of the ground traces such that the given ground trace overlap multiple ground traces of another one of the sets.

10 . The method of claim 8 , wherein coupling the ground traces comprises providing vias to couple the given ground trace to the multiple ground traces overlapped by the given ground trace.

11 . The method of claim 7 , wherein the providing the ground traces comprises embedding at least some of the ground traces in at least one layer of the penetration detection boundary.

12 . A system comprising:

a processor to store at least one security key; and

a substrate comprising:

a first metal layer to communicate signals for the processor; and

a plurality of additional metal layers, wherein each of the plurality of additional metal layers comprise an associated trace arranged in a tortuous pattern to detect penetration of the metal layer and an associated ground trace; and

vias to electrically couple to the ground traces together to form a heat sink to dissipate power for the processor.

13 . The system of claim 12 , further comprising a circuit coupled to provide a signal to at least one of the traces arranged in a tortuous pattern and detect interruption of the signal to detect penetration of the associated metal layer.

14 . The system of claim 12 , further comprising another metal layer comprising a ground plane, wherein at least one of the vias electrically couples the ground plane and the ground traces together.

15 . The system of claim 12 , wherein:

the tortuous pattern comprises folds; and

at least some of the ground traces are disposed in the folds.