Image capturing method and image capturing apparatus

1. An image capturing method for an image capturing apparatus having a color-separation optical system and three or more CMOS image capturing elements, comprising:

capturing a plurality of image frames of B at a speed of an integer N multiple of a number of output picture frames, capturing a plurality of image frames of G, or G 1 and G 2 , at a speed of an integer M multiple of an integer N+1 or more, and capturing a plurality of image frames of R at a speed of the integer M multiple of the integer N+1 or more;

offsetting vertical synchronization phases of the captured image frames of B, G, and R, or B, G 1 , G 2 , and R, which are to be used for an output picture by approximately half a vertical synchronization period of an even multiple of speed such that each center phase of the captured image frames of B, G, and R, or B, G 1 , G 2 , and R, has approximately a same vertical synchronization phase; and

using, for the output picture, vertical effective pictures of the captured image frames of B, G, and R, or B, G 1 , G 2 , and R, having approximately the same vertical synchronization phase,

wherein the image capturing method comprises at least one of the group consisting of:

(a) generating and feeding a vertical synchronization signal derived from offsetting the center phase by approximately half the center phase at substantially X2 speed to a CMOS image capturing element of R at X2 speed for image capturing at X2 speed, generating and feeding a vertical synchronization signal derived from aligning the center phase at X3 speed to a CMOS image capturing element of G, or G 1 and G 2 , for image capturing at X3 speed, and generating and feeding a vertical synchronization pulse derived from aligning the center phase at the equal speed to a CMOS image capturing element of B for image capturing at the equal speed;

(b) generating and feeding a vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of R at X2 speed for image capturing at X2 speed, generating and feeding a vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of G, or G 1 and G 2 , at X2 speed for image capturing at X2 speed, and generating and feeding a vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of B at the equal speed for image capturing at the equal speed;

(c) generating and feeding a vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of R at X3 speed for image capturing at X3 speed, generating and feeding a vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X4 speed to the CMOS image capturing element of G, or G 1 and G 2 , at X4 speed for image capturing at X4 speed, and generating and feeding a vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of B at X2 speed for image capturing at X2 speed; and

(d) generating and feeding a vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X4 speed to the CMOS image capturing element of R at X4 speed for image capturing at X4 speed, generating and feeding a vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X4 speed to the CMOS image capturing element of G 1 and G 2 , or G at X4 speed for image capturing at X4 speed, and generating and feeding a vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of B at X2 speed for image capturing at X2 speed.

2. An image capturing apparatus including a color-separation optical system and CMOS image capturing elements as three or more focal plane shutters, comprising:

a timing circuit which generates and applies a vertical synchronization signal derived from offsetting vertical synchronization phases of captured image frames of B, G, and R, or B, G 1 , G 2 , and R, by approximately half a vertical synchronization period at an even multiple of speed, and generates a vertical synchronization signal without offsetting the vertical synchronization period at an odd multiple of speed;

a CMOS image capturing element for image capturing of B at a speed of an integer N multiple of a number of output picture frames in synchronization with the vertical synchronization signal derived from offsetting by approximately half the vertical synchronization period at an even multiple of speed;

a CMOS image capturing element for image capturing of G, or G 1 and G 2 , at a speed of an integer M multiple of an integer N+1 or more in synchronization with the vertical synchronization signal without offsetting the vertical synchronization period at an odd multiple of speed;

a CMOS image capturing element for image capturing of R at a speed of the integer M multiple of the number of the integer N+1 or more in synchronization with the vertical synchronization signal without offsetting the vertical synchronization period at the odd multiple of speed; and

a picture signal processing circuit including frame speed conversion means,

wherein the image capturing apparatus comprises at least one of the group consisting of:

(a) the timing circuit which generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of R at X2 speed, generates and feeds the vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of G, or G 1 and G 2 , at X3 speed, generates and feeds the vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of B at the equal speed, and the CMOS image capturing element of R executes image capturing at X2 speed, the CMOS image capturing element of G, or G 1 and G 2 , executes image capturing at X3 speed, and the CMOS image capturing element of B executes image capturing at the equal speed;

(b) the timing circuit which generates and feeds the vertical synchronization signal derived from offsetting the center phase by half the frame at substantially X2 speed to the CMOS image capturing element of R at X2 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of G, or G 1 and G 2 , at X2 speed, generates and feeds the vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of B at the equal speed, and the CMOS image capturing element of R executes image capturing at X2 speed, the CMOS image capturing element of G, or G 1 and G 2 , executes image capturing at X2 speed, and the CMOS image capturing element of B executes image capturing at the equal speed;

(c) the timing circuit generates and feeds the vertical synchronization signal derived from aligning the center phase to the CMOS image capturing element of R at X3 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X4 speed to the CMOS image capturing element of G, or G 1 and G 2 , at X4 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X2 speed to the CMOS image capturing element of B at X2 speed, and the CMOS image capturing element of R executes image capturing at X3 speed, the CMOS image capturing element of G, or G 1 and G 2 , executes image capturing at X4 speed, and the CMOS image capturing element of B executes image capturing at X2 speed; and

(d) the timing circuit which generates and feeds the vertical synchronization signal derived from offsetting the center phase by approximately half the frame at substantially X4 speed to the CMOS image capturing element of R at X4 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by half the frame at substantially X4 speed to the CMOS image capturing element of G, or G 1 and G 2 , at X4 speed, generates and feeds the vertical synchronization signal derived from offsetting the center phase by half the frame at substantially X2 speed to the CMOS image capturing element of B at X2 speed, and the CMOS image capturing element of R executes image capturing at X4 speed, the CMOS image capturing element of G, or G 1 and G 2 , executes image capturing at X4 speed, and the CMOS image capturing element of B executes image capturing at X2 speed.