Granted Patent B2

US 9,854,200 · App. 15/514,949 · Granted Dec 26, 2017

Abstract

Claims (34)

1. A video display device, comprising:

a display including a plurality of pixel portions that are arranged in a matrix having n rows and m columns;

a processor;

a memory including instructions that, when executed by the processor, cause the processor to perform operations including:

obtaining a video represented in an input video format for displaying, at a predetermined frame frequency, a plurality of frames each including an effective pixel region having n rows and m columns, p 1 columns of a horizontal blanking period, and q 1 rows of a vertical blanking period;

converting a format of the video to an output video format for displaying, at the predetermined frame frequency, a plurality of frames each including the effective pixel region having n rows and m columns, p 2 columns of the horizontal blanking period, and q 2 rows of the vertical blanking period, where q 2 is less than q 1 ; and

a display driver configured to display the video row by row in the display at a horizontal scanning frequency in the output video format,

wherein the operations further include:

storing the video for each frame in a frame memory;

generating a horizontal synchronization signal at the horizontal scanning frequency indicated by f HSYNC2 and a dot clock signal at a dot frequency indicated by f DCLK2 based on relationships f HSYNC2 =f 1F (n+q 2 ) and f DCLK2 =f 1F (m+p 2 )(n+q 2 ), where f 1F denotes the predetermined frame frequency; and

reading out video data for each pixel from the frame memory based on the dot clock signal, and supplying the video data that has been read out and the horizontal synchronization signal to the display driver, and

the display driver is further configured to sequentially drive, row by row, a display operation in the pixel portions disposed in one of the rows of the display in synchronization with the horizontal synchronization signal.

2. The video display device according to claim 1 ,

wherein the processor is configured to convert the format of the video to the output video format that satisfies a relationship (m+p 1 )(n+q 1 )=(m+p 2 )(n+q 2 ).

3. The video display device according to claim 1 ,

wherein the processor is configured to convert the format of the video to the output video format that satisfies a relationship (m+p 1 )(n+q 1 )=(m+p 2 )n, q 2 =0.

4. A video display method, comprising:

obtaining a video represented in an input video format for displaying, at a predetermined frame frequency, a plurality of frames each including an effective pixel region having n rows and m columns, p 1 columns of a horizontal blanking period, and q 1 rows of a vertical blanking period;

converting a format of the video to an output video format for displaying, at the predetermined frame frequency, a plurality of frames each including the effective pixel region having n rows and m columns, p 2 columns of the horizontal blanking period, and q 2 rows of the vertical blanking period, where q 2 is less than q 1 ; and

displaying the video row by row in a display at a horizontal scanning frequency in the output video format, the display including a plurality of pixel portions that are arranged in a matrix having n rows and m columns,

wherein the converting includes:

storing the video for each frame in a frame memory;

generating a horizontal synchronization signal at the horizontal scanning frequency indicated by f HSYNC2 and a dot clock signal at a dot frequency indicated by f DCLK2 based on relationships f HSYNC2 =f 1F (n+q 2 ) and f DCLK2 =f 1F (m+p 2 )(n+q 2 ), where f 1F denotes the predetermined frame frequency; and

reading out video data for each pixel from the frame memory based on the dot clock signal, and supplying the video data that has been read out and the horizontal synchronization signal to a display driver, and

the displaying includes sequentially driving, by the display driver and row by row, a display operation in the pixel portions disposed in one of the rows of the display in synchronization with the horizontal synchronization signal.

5. A non-transitory computer-readable recording medium that stores a program that, when executed by a computer, causes a computer to execute a video display method, the video display method comprising:

obtaining a video represented in an input video format for displaying, at a predetermined frame frequency, a plurality of frames each including an effective pixel region having n rows and m columns, p 1 columns of a horizontal blanking period, and q 1 rows of a vertical blanking period;

converting a format of the video to an output video format for displaying, at the predetermined frame frequency, a plurality of frames each including the effective pixel region having n rows and m columns, p 2 columns of the horizontal blanking period, and q 2 rows of the vertical blanking period, where q 2 is less than q 1 ; and

displaying the video row by row in a display at a horizontal scanning frequency in the output video format, the display including a plurality of pixel portions that are arranged in a matrix having n rows and m columns,

wherein the converting includes:

storing the video for each frame in a frame memory;

generating a horizontal synchronization signal at the horizontal scanning frequency indicated by f HSYNC2 and a dot clock signal at a dot frequency indicated by f DCLK2 based on relationships f HSYNC2 =f 1F (n+q 2 ) and f DCLK2 =f 1F (m+p 2 )(n+q 2 ), where f 1F denotes the predetermined frame frequency; and

reading out video data for each pixel from the frame memory based on the dot clock signal, and supplying the video data that has been read out and the horizontal synchronization signal to a display driver, and

the displaying includes sequentially driving, by the display driver and row by row, a display operation in the pixel portions disposed in one of the rows of the display in synchronization with the horizontal synchronization signal.

Assignments (6)