Method for manufacturing at least one optoelectronic semiconductor chip
View Patent ↗Disclosed is an optoelectronic semiconductor chip ( 10 ) comprising: —a succession of semiconductor layers ( 1 ) that has a main plane of extension, an active layer ( 12 ) and a bottom surface ( 1 c ); —a substrate ( 41 ) that is arranged on the bottom surface ( 1 c ) of the succession of semiconductor layers ( 1 ) and has a base surface ( 41 c ) facing away from the bottom surface ( 1 c ); and —a succession of joining layers ( 3 ) which is arranged in at least some locations between the succession of semiconductor layers ( 1 ) and the substrate ( 41 ) in a vertical direction; wherein —the substrate ( 41 ) laterally protrudes from the succession of semiconductor layers ( 1 ) by a maximum of 10 μm.
1. A method for manufacturing at least one optoelectronic semiconductor chip having the following steps:
a) providing a laminar structure comprising
a semiconductor layer sequence with a main extension plane, an active layer and a bottom surface,
a carrier, which is arranged on the bottom surface of the semiconductor layer sequence and comprises a base surface facing away from the bottom surface, and
a connecting layer sequence, which is arranged between the semiconductor layer sequence and the carrier in a vertical direction, at least in some areas,
b) forming a plurality of separation trenches in the laminar structure along a singulation pattern using at least one directional dry etching method, wherein
at least one separation trench has a maximum extension of no more than 30 μm in at least one lateral direction and
each separation trench completely penetrates the laminar structure in the vertical direction,
c) singulating the laminar structure along the separation trenches to produce at least one optoelectronic semiconductor chip, wherein the at least one singulated optoelectronic semiconductor chip comprises in each case a part of the semiconductor layer sequence, of the carrier and of the connecting layer sequence, wherein the formation of the separation trenches in step b) comprises the following steps:
b1) partial removal of the semiconductor layer sequence in the region of the separation trenches to be produced,
b2) partial removal of the connecting layer sequence in the region of the partially removed semiconductor layer sequence,
b3) application of an ALD layer to all exposed external surfaces of the laminar structure facing away from the base surface,
b4) partial removal of the ALD layer from a carrier top surface of the carrier facing away from the base surface in the region of the separation trenches to be produced,
b5) partial removal of the carrier in the region of the partially removed semiconductor layer sequence and of the partially removed connecting layer sequence, wherein for steps b1), b2) and b5) a dry etching method is at least partially used.
2. The method according to claim 1 ,
wherein the ALD layer in step b4) is removed from all exposed external surfaces of the semiconductor layer sequence, of the singulation pattern and/or of the carrier running along the main extension plane within the limits of manufacturing tolerances.
3. The method according to claim 1 ,
wherein the laminar structure furthermore comprises a radiation-reflecting contact layer sequence with a metal layer arranged between the connecting layer sequence and the semiconductor layer sequence, wherein the metal layer is removed to produce the separation trenches in step b) with partial use of a wet chemical etching method.
4. The method according to claim 3 ,
wherein all exposed external surfaces of the semiconductor layer sequence are cleaned in step b) and/or after step c) in such a way that traces of a material of the connecting layer sequence and/or of the contact layer sequence are removed from the exposed external surfaces of the semiconductor layer sequence.
5. A method for manufacturing at least one optoelectronic semiconductor chip having the following steps:
a) providing a laminar structure comprising
a semiconductor layer sequence with a main extension plane, an active layer and a bottom surface,
a carrier, which is arranged on the bottom surface of the semiconductor layer sequence and comprises a base surface facing away from the bottom surface, and
a connecting layer sequence, which is arranged between the semiconductor layer sequence and the carrier in a vertical direction, at least in some areas,
b) forming a plurality of separation trenches in the laminar structure along a singulation pattern using at least one directional dry etching method, wherein
at least one separation trench has a maximum extension of no more than 30 μm in at least one lateral direction and
each separation trench completely penetrates the laminar structure in the vertical direction,
c) singulating the laminar structure along the separation trenches to produce at least one optoelectronic semiconductor chip, wherein the at least one singulated optoelectronic semiconductor chip comprises in each case a part of the semiconductor layer sequence, of the carrier and of the connecting layer sequence,
wherein the laminar structure furthermore comprises a radiation-reflecting contact layer sequence with a metal layer arranged between the connecting layer sequence and the semiconductor layer sequence, wherein the metal layer is removed to produce the separation trenches in step b) with partial use of a wet chemical etching method.
6. The method according to claim 5 ,
wherein all exposed external surfaces of the semiconductor layer sequence are cleaned in step b) and/or after step c) in such a way that traces of a material of the connecting layer sequence and/or of the contact layer sequence are removed from the exposed external surfaces of the semiconductor layer sequence.