Lateral insulated-gate bipolar transistor
A lateral insulated gate bipolar transistor comprises a substrate ( 10 ); an anode terminal located on the substrate, comprising: an N-type buffer region ( 51 ) located on the substrate ( 10 ); a P well ( 53 ) located in the N-type buffer region; an N-region ( 55 ) located in the P well ( 53 ); two P+ shallow junctions ( 57 ) located on a surface of the P well ( 53 ); and an N+ shallow junction ( 59 ) located between the two P+ shallow junctions ( 57 ); a cathode terminal located on the substrate; a draft region ( 30 ) between the anode terminal and cathode terminal; and a gate ( 62 ) between the anode terminal and cathode terminal.
1. A lateral insulated gate bipolar transistor, comprising:
a substrate;
an anode terminal located on the substrate, comprising:
an N-type buffer region located on the substrate;
a P well located in the N-type buffer region;
an N-region located in the P well;
two P+ shallow junctions located on a surface of the P well; and
an N+ shallow junction located between the two P+ shallow junctions;
a cathode terminal located on the substrate;
a drift region between the anode terminal and cathode terminal; and
a gate between the anode terminal and cathode terminal.
2. The lateral insulated gate bipolar transistor of claim 1 , characterized in that, a doped concentration of the N-type buffer region is less than a doped concentration of the P well; the doped concentration of the P well is less than a doped concentration of the N-region; and the doped concentration of the N-region is less than doped concentrations of the two P+ shallow junctions and the N+ shallow junction.
3. The lateral insulated gate bipolar transistor of claim 2 , characterized in that, the doped concentration of the N-type buffer region is from 1*10 15 /cm 3 to 1*10 16 /cm 3 ; the doped concentration of the P well is from 1*10 17 /cm 3 to 1*10 18 /cm 3 ; and the doped concentrations of the two P+ shallow junctions and the N+ shallow junction are from 1*10 20 /cm 3 to 1*10 21 /cm 3 .
4. The lateral insulated gate bipolar transistor of claim 3 , characterized in that, the doped concentration of the N-type buffer region is 5*10 15 /cm 3 ; and the doped concentration of the P well is 8*10 17 /cm 3 .
5. The lateral insulated gate bipolar transistor of claim 1 , characterized in that, the lateral insulated gate bipolar transistor is a silicon-on-insulator type lateral insulated gate bipolar transistor, and the lateral insulated gate bipolar transistor further comprises a buried oxide layer located between the substrate and the drift region.
6. The lateral insulated gate bipolar transistor of claim 1 , characterized in that, the substrate is a P-type substrate; and the drift region is an N-type drift region.
7. The lateral insulated gate bipolar transistor of claim 6 , characterized in that, the cathode terminal comprises:
a P+ region located on the substrate;
a P-type body region located between the P+ region and the anode terminal; and
an N+ region located at a surface of the P-type body region.
8. The lateral insulated gate bipolar transistor of claim 7 , characterized in that, the P+ region extends to the buried oxide layer.
9. The lateral insulated gate bipolar transistor of claim 7 , characterized in that, the anode terminal further comprises an anode metal; the cathode terminal further comprises a cathode metal; and the gate comprises a gate oxide layer and a polysilicon gate on the gate oxide layer.
10. The lateral insulated gate bipolar transistor of claim 1 , characterized in that, one of two P+ shallow junctions that is positioned closer to the cathode terminal and the N+ shallow junction are disposed at a surface of the N-region.