IP Library Granted Patent US 10,452,557
Granted Patent B2
US 10,452,557 · App. 15/540,042 · Granted Oct 22, 2019

Storage apparatus, computer system, and method for improved read operation handling

Inventors: Hirotoshi Akaike (Tokyo, JP); Norio Shimozono (Tokyo, JP); Kazushi Nakagawa (Tokyo, JP)
Assignee: Hitachi, Ltd.
G06F12/10G06F3/061G06F3/0635G06F3/0659G06F3/0688G06F12/0246G06F2212/657G06F2212/7201G06F2212/7202
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Quick Facts
Patent No.
US 10,452,557
App. No.
15/540,042
Granted
Oct 22, 2019
Kind
B2
Abstract

The processor provides a host computer with a logical volume based on a physical storage device. Based on a command from the host computer, the control device writes, into a memory, address information that associates a logical address in the logical volume with a device address in the physical storage device. The control device receives a command from the host computer and if it is determined that the command is a read command, identifies a first logical address designated by the command and determines whether or not the first logical address is included in the address information. If the first address is included in the address information, the control device specifies a first device address corresponding to the first logical address, reads read data stored in an area indicated by the first device address, and transmits the read data to the host computer.

Claims (86)

1. A storage apparatus, comprising:

a controller coupled to a host computer; and

a physical storage device coupled to the controller, wherein

the controller includes:

a processor configured to provide the host computer with a logical volume based on the physical storage device;

a first memory coupled to the processor;

a control device coupled to the host computer, the physical storage device, and the processor; and

a second memory coupled to the control device,

the control device writes into the second memory, according to an entry registration command from the processor, address information that associates a logical address in the logical volume with a device address, which is an address in the physical storage device,

the control device, upon receiving a command from the host computer:

determines whether or not the command is a read command, and when determination is made that the command is a read command, identifies a first logical address designated by the read command and determines whether or not the first logical address is included in the address information,

when the first logical address is included in the address information, specifies a first device address corresponding to the first logical address,

reads read data stored in an area indicated by the first device address and transmits the read data to the host computer,

when the first logical address is not included in the address information, transmits the command to the processor, and

when determination is made that the command is a command other than a read command, transmits the command to the processor, and

the processor executes a process designated by the command received from the control device.

2. The storage apparatus according to claim 1 , wherein

the processor is configured to,

when receiving the read command, identify the first logical address designated by the read command and transmit the read data indicated by the first logical address to the host computer.

3. The storage apparatus according to claim 2 , wherein

the first memory is configured to store conversion information for specifying the device address from the logical address,

the processor is configured to

determine whether or not dirty data is stored in a cache area of the first memory based on the first logical address designated by the read command,

when the dirty data is not stored in the cache area, specify a first device address corresponding to the first logical address, based on the conversion information,

read data stored in an area indicated by the first device address to the cache area and transmit the read data to the host computer, and

transmit the first logical address and the first device address to the control device, and

the control device is configured to

receive the first logical address and the first device address, and register in the address information the first logical address and the first device address in association with each other.

4. The storage apparatus according to claim 3 , wherein

the processor is configured to, when read data that is clean data is stored in the cache area based on the first logical address designated by the read command or when the read data is not stored in the cache area, determine that dirty data is not stored in the cache area.

5. The storage apparatus according to claim 4 , wherein

the control device is configured to:

when the command is determined to be a write command, determine whether or not a second logical address of the logical volume designated by the write command is registered in the address information,

when the second logical address is registered in the address information, delete the second logical address from the address information, and

transmit the write command to the processor.

6. The storage apparatus according to claim 5 , wherein

the processor is configured to:

receive write data based on the write command,

specify a second device address corresponding to the second logical address, based on information in the first memory,

store the write data in a cache area of the first memory and also in an area indicated by the second device address, and

transmit a response based on the write command to the host computer.

7. The storage apparatus according to claim 4 , wherein

the processor is configured to:

monitor a load on the processor,

when read data that is the clean data is stored in the cache area and in an area indicated by the first address, determine whether or not the load is larger than a threshold configured in advance,

when the load is larger than the threshold, transmit the read data to the host computer, and

transmit the first logical address and the first device address to the control device, and

the control device is configured to:

receive the first logical address and the first device address, and register in the address information the first logical address and the first device address in association with each other.

8. The storage apparatus according to claim 7 , wherein

the processor is configured to:

with respect to a logical address consecutive to the first logical address in the logical volume designated by the read command, when a look-ahead process, in which read data stored in an area of a physical storage device corresponding to the logical volume is read in advance, is being executed,

delete a third device address of an area storing data to be read by the look-ahead process from the address information.

9. The storage apparatus according to claim 1 , wherein

the physical storage device is a non-volatile semiconductor memory.

10. The storage apparatus according to claim 1 , wherein

the control device is configured to create a plurality of sorted queues in the second memory,

the plurality of sorted queues respectively correspond to a plurality of logical addresses,

the control device is configured to, in a command sorting process:

when receiving the command from the host computer, determine whether or not the command is an IO (Input or Output) command,

when determination is made that the command is an IO command, identify a first logical address in the logical volume designated by the IO command,

select a first sorted queue corresponding to the first logical address from the plurality of sorted queues, and

enqueue the IO command to the first sorted queue, and

the control device is configured to dequeue the IO command in the first sorted queue and execute a process designated by the IO command.

11. The storage apparatus according to claim 10 , wherein

the control device is configured to,

when determination is made that the command is not the IO command in the command sorting process, enqueue the command to a second sorted queue configured in advance from the plurality of sorted queues, and

dequeue the command in the second sorted queue and transmit the command to the processor.

12. The storage apparatus according to claim 11 , wherein

the control device is configured to, when determination is made that the IO command is a read command in the command sorting process, perform a plurality of command processes in parallel.

13. The storage apparatus according to claim 11 , wherein

the control device is capable of executing a plurality of individual command processes for executing a single command in the command process, and

the control device is configured to, when determination is made that the IO command is a read command in the command process, execute the first individual command process with respect to the read command when a state is established in which at least one individual command process among the plurality of individual command processes is not being executed.

14. The storage apparatus according to claim 13 , wherein

the control device is configured to, when determination is made that the command is a write command in the command process, execute an individual command process with respect to the write command when a state is established in which all of the plurality of individual command processes are not being executed.

15. A method executed by the controller including a processor which provides a host computer with a logical volume based on a physical storage device and a control device coupled to the host computer, the physical storage device, and the processor,

the method comprising, with the use of the control device:

writing into the second memory, according to an entry registration command from the processor, address information that associates a logical address in the logical volume, with a device address, which is an address in the physical storage device;

upon receiving a command from the host computer,

determining whether or not the command is a read command, and when determination is made that the command is a read command, identifying a first logical address designated by the command and determine whether or not the first logical address is included in the address information;

when the first logical address is included in the address information, specifying a first device address corresponding to the first logical address;

reading read data stored in an area indicated by the first device address and transmitting the read data to the host computer;

when the first logical address is not included in the address information, transmitting the command to the processor; and

when determination is made that the command is a command other than a read command, transmitting the command to the processor; and

with the use of the processor

executing a process designated by the command received from the control device.

Assignments (2)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2017
From: AKAIKE, HIROTOSHI; SHIMOZONO, NORIO; NAKAGAWA, KAZUSHI
To: HITACHI, LTD.
Reel/Frame 042821/0688 →
Continuity (1)
Related Publication 20180018272A1 · Jan 18, 2018