IP Library Granted Patent US 10,467,176
Granted Patent B2
US 10,467,176 · App. 15/545,461 · Granted Nov 5, 2019

Information processing apparatus

Inventors: Satoshi Morishita (Tokyo, JP); Mitsuhiro Okada (Tokyo, JP); Akifumi Suzuki (Tokyo, JP); Shimpei Nomura (Tokyo, JP)
Assignee: Hitachi, Ltd.
G06F13/4221G06F3/067G06F3/0613G06F3/0635G06F3/0658G06F12/0215G06F13/00G06F13/10G06F13/12G06F13/126G06F13/14G06F13/4022G06F2213/0026
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Quick Facts
Patent No.
US 10,467,176
App. No.
15/545,461
Granted
Nov 5, 2019
Kind
B2
Abstract

An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.

Claims (11)

1. An information processing apparatus, comprising:

a processor;

a memory;

at least one accelerator;

at least one storage device; and

a network configured to couple the processor, the at least one accelerator, and the at least one storage device to one another,

wherein the at least one storage device comprises:

an I/O interface configured to receive an I/O command, and

wherein the processor is configured to collect information on at least one storage device and at least one accelerator, which are coupled to the network, and to store the information into the memory as network configuration information,

wherein the processor is configured to derive an assignment of the at least one storage device and the at least one accelerator that satisfies a predetermined condition based on the network configuration information, and

wherein the processor is configured to notify the at least one accelerator of one of an address of an initial setting interface of the at least one storage device and an address of the I/O interface of the at least one storage device based on the derived assignment.

Assignments (2)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2017
From: MORISHITA, SATOSHI; OKADA, MITSUHIRO; SUZUKI, AKIFUMI; NOMURA, SHIMPEI
To: HITACHI, LTD.
Reel/Frame 043063/0666 →
Continuity (1)
Related Publication 20180011812A1 · Jan 11, 2018
Cited By (2)
US 12,572,300 US 12,632,405