Method for producing a plurality of semiconductor chips and semiconductor chip
Disclosed is a method for producing a plurality of semiconductor chips ( 10 ). A composite ( 1 ), which comprises a carrier ( 4 ) and a semiconductor layer sequence ( 2, 3 ), is provided. Separating trenches ( 17 ) are formed in the semiconductor layer sequence ( 2, 3 ) along an isolation pattern ( 16 ). A filling layer ( 11 ) limiting the semiconductor layer sequence ( 2, 3 ) toward the separating trenches ( 17 ) is applied to a side of the semiconductor layer sequence ( 2, 3 ) facing away from the carrier ( 4 ). Furthermore, a metal layer ( 10 ) adjacent to the filling layer ( 11 ) is applied in the separating trenches ( 17 ). The semiconductor chips ( 20 ) are isolated by removing the metal layer ( 10 ) adjacent to the filling layer ( 11 ) in the separating trenches ( 17 ). Each isolated semiconductor chip ( 20 ) has one part of the semiconductor layer sequence ( 2, 3 ), and of the filling layer ( 11 ). Also disclosed is a semiconductor chip ( 10 ).
1. Method of producing a plurality of semiconductor chips, having the method steps:
a) providing a composite structure, which comprises a carrier and a semiconductor layer sequence;
b) forming dicing trenches in the semiconductor layer sequence along a singulation pattern;
c) applying a filling layer delimiting the semiconductor layer sequence relative to the dicing trenches on a side of the semiconductor layer sequence remote from the carrier;
d) applying a metal layer, adjoining the filling layer, in the dicing trenches; and
e) singulating the semiconductor chips by removing the metal layer adjoining the filling layer from the dicing trenches;
wherein the singulated semiconductor chips each comprise one part of the semiconductor layer sequence and the filling layer, and wherein the composite structure is attached to an auxiliary carrier prior to singulation and the semiconductor chips are present in a geometric arrangement on the auxiliary carrier after singulation.
2. Method according to claim 1 ,
in which in step d) the metal layer is additionally applied on a side of the filling layer remote from the dicing trenches on a side of the semiconductor layer sequence remote from the carrier.
3. Method according to claim 1 ,
in which the metal layer is applied at least in part by an electroplating method.
4. Method according to claim 1 ,
in which the metal layer adjoining the filling layer is removed from the dicing trenches using a chemical method.
5. Method according to claim 1 ,
in which the dicing trenches are formed using a chemical method.
6. Method according to claim 1 ,
in which, after step b), the dicing trenches extend right through the semiconductor layer sequence.
7. Method according to claim 1 ,
in which detachment of the carrier is performed in an additional step.
8. Method of producing a plurality of semiconductor chips, having the method steps:
a) providing a composite structure, which comprises a carrier and a semiconductor layer sequence;
b) forming dicing trenches in the semiconductor layer sequence along a singulation pattern;
c) forming dicing strips by applying a metal layer in the dicing trenches;
d) applying a filling layer delimiting the semiconductor layer sequence relative to the dicing trenches on a side of the semiconductor layer sequence remote from the carrier;
e) removing the dicing strips in the trenches;
f) attaching the composite structure to an auxiliary carrier; and
g) singulating the semiconductor chips by removing the carrier, wherein the singulated semiconductor chips each comprise one part of the semiconductor layer sequence and the filling layer, and wherein the semiconductor chips are present in a geometric arrangement on the auxiliary carrier after singulation.
9. Method according to claim 8 ,
in which the metal layer is applied at least in part by an electroplating method.
10. Method according to claim 8 ,
in which the metal layer adjoining the filling layer is removed from the dicing trenches using a chemical method.
11. Method according to claim 8 ,
in which the dicing trenches are formed using a chemical method.
12. Method according to claim 8 ,
in which, after step b), the dicing trenches extend right through the semiconductor layer sequence.