System and a method for determining a correction for an output value of a time-to-digital converter within a phase-locked loop

1. A system for determining a correction for an output value of a time-to-digital converter within a phase-locked loop, the output value relating to a time difference between an input signal and a reference signal supplied to the time-to-digital converter, comprising:

a digitally-controlled oscillator configured to generate a first signal independently from the output value, wherein the first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal;

a frequency divider configured to generate the input signal for the time-to-digital converter based on the first signal, wherein the input signal has a second frequency being a fraction of the first frequency; and

a processing unit configured to calculate the correction using a distribution of output values of multiple time differences.

2. The system of claim 1 , wherein the frequency divider is configured to select a ratio of the second frequency to the first frequency based on a control signal, and wherein the control signal is based on the output value.

3. The system of claim 2 , wherein the system further comprises:

a comparator configured to compare the output value to a threshold; and

a signal modification unit configured to modify a constant signal based on a comparison result of the comparator to provide the control signal.

4. The system of claim 3 , wherein the signal modification unit is configured to linearly modify a value represented by the constant signal by an offset value for an oscillation period of the input signal.

5. The system of claim 4 , further comprising an offset provision unit configured to supply the offset value to the signal modification unit based on the comparison result of the comparator.

6. The system of claim 3 , wherein the frequency divider comprises a multi-modulus divider, and wherein the system further comprises a sigma-delta modulator configured to generate the constant signal independently from a second input signal provided to the sigma-delta modulator.

7. The system of claim 1 , wherein an absolute value of a difference between a ratio of the first frequency to the reference frequency and a ratio of the integer multiple of the reference frequency to the reference frequency is smaller than about 0.05.

8. The system of claim 1 , wherein the processing unit comprises an integrator configured to integrate the distribution of output values.

9. The system of claim 8 , wherein the processing unit is further configured to collect the distribution of output values in bins of a histogram, the bins corresponding to a predetermined range of the output values, and wherein the integrator is further configured to integrate contents of the bins.

10. The system of claim 1 , wherein the system further comprises a loop filter configured to receive the output value, and wherein the loop filter is further configured to generate a further control signal for the digitally-controlled oscillator independently from the output value.

11. A system for modifying an output value of a time-to-digital converter within a phase-locked loop, the output value relating to a time difference between an input signal and a reference signal supplied to the time-to-digital converter, comprising:

a digitally-controlled oscillator configured to generate a first signal independently from the output value in a first mode of operation, wherein the first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal;

a frequency divider configured to generate, in the first mode, the input signal for the time-to-digital converter based on the first signal, wherein the input signal has a second frequency being a fraction of the first frequency;

a processing unit configured to calculate, in the first mode, a correction for the output value using a distribution of output values of multiple time differences,

wherein the digitally-controlled oscillator is configured to generate, depending on the output value, a second signal in a second mode of operation,

wherein the frequency divider is configured to generate, in the second mode, the input signal based on the second signal, wherein the second frequency is a fraction of the frequency of the second signal; and

a correction unit configured to modify, in the second mode, the output value by the correction.

12. The system of claim 11 , further comprising a loop-up table configured to receive, in the first mode, the correction and to supply, in the second mode, the correction to the correction unit.

13. A method for determining a correction for an output value of a time-to-digital converter within a phase-locked loop, the output value relating to a time difference between an input signal and a reference signal supplied to the time-to-digital converter, comprising:

generating a first signal independently from the output value, wherein the first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal;

generating the input signal for the time-to-digital converter based on the first signal, wherein the input signal has a second frequency being a fraction of the first frequency; and

calculating the correction using a distribution of output values of multiple time differences.

14. The method of claim 13 , wherein generating the input signal for the time-to-digital converter comprises selecting a ratio of the second frequency to the first frequency based on a control signal, and wherein the control signal is based on the output value.

15. The method of claim 14 , wherein generating the input signal comprises:

comparing the output value to a threshold; and

modifying a constant signal based on a comparison result to provide the control signal.

16. The method of claim 15 , wherein modifying the constant signal comprises linearly modifying a value represented by the constant signal by an offset value for an oscillation period of the input signal.

17. The method of claim 13 , wherein an absolute value of a difference between a ratio of the first frequency to the reference frequency and a ratio of the integer multiple of the reference frequency to the reference frequency is smaller than about 0.05.

18. The method of claim 13 , wherein calculating the correction comprises integrating the distribution of output values.

19. The method of claim 18 , wherein integrating the distribution of output values comprises:

collecting the distribution of output values in bins of a histogram, the bins corresponding to a predetermined range of output values; and

integrating contents of the bins.

20. A method for modifying an output value of a time-to-digital converter within a phase-locked loop, the output value relating to a time difference between an input signal and a reference signal supplied to the time-to-digital converter, comprising:

calculating a correction for the output value in a first mode of operation, wherein calculating the correction comprises:

generating a first signal independently from the output value, wherein the first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal;

generating the input signal for the time-to-digital converter based on the first signal, wherein the input signal has a second frequency being a fraction of the first frequency;

calculating the correction using a distribution of output values of multiple time differences;

generating, depending on the output value, a second signal in a second mode of operation;

generating, in the second mode, the input signal based on the second signal, wherein the second frequency is a fraction of the frequency of the second signal; and

modifying, in the second mode, the output value by the correction.