Virtual debugging of server operations
Debugging operations may utilize a dedicated debug port associated with a baseboard management controller. The baseboard management controller executes software programming that eliminates any need for a debugging cable. The baseboard management controller also permits debugging between virtual machines.
1. A method, comprising:
emulating, by a baseboard management controller, a debug cable as a virtual debug cable;
emulating, by the baseboard management controller, a first virtual debug device via a first input/output port;
emulating, by the baseboard management controller, a second virtual debug device via a second input/output port; and
bridging, by the baseboard management controller, data passing from the first virtual debug device to the second virtual debug device during a debug operation.
2. The method of claim 1 , further comprising redirecting the data from the first input/output port to the second input/output port.
3. The method of claim 1 , further comprising redirecting the data from a universal serial bus interface to another universal serial bus interface.
4. The method of claim 1 , further comprising redirecting the data output from the first input/output port to an input at the second input/output port.
5. The method of claim 1 , further comprising redirecting the data input at the first input/output port to an output to the second input/output port.
6. The method of claim 1 , further comprising debugging the first virtual debug device.
7. The method of claim 1 , further comprising debugging the second virtual debug device.
8. An information handling system, comprising:
a processor; and
a memory device accessible to the processor, the memory device storing instructions, the instructions when executed causing the processor to perform operations including:
emulating a debug cable as a virtual debug cable virtually connected between a first virtual debug device and a first input/output port to a baseboard management controller;
emulating a second virtual debug device at a second input/output port to the baseboard management controller; and
bridging data passing from the first virtual debug device through the baseboard management controller to the second virtual debug device during a debug operation.
9. The system of claim 8 , wherein the operations further comprise redirecting the data from the first input/output port to the second input/output port.
10. The system of claim 8 , wherein the operations further comprise redirecting the data from a universal serial bus interface at the first input/output port to another universal serial bus interface at the second input/output port.
11. The system of claim 8 , wherein the operations further comprise redirecting the data output from the first input/output port to an input at the second input/output port.
12. The system of claim 8 , wherein the operations further comprise redirecting the data input at the first input/output port to an output to the second input/output port.
13. The system of claim 8 , wherein the operations further comprise debugging the first virtual debug device.
14. The system of claim 8 , wherein the operations further comprise debugging the second virtual debug device.
15. A memory device storing instructions that when executed cause a processor to perform operations, the operations comprising:
emulating a physical debug cable as a virtual debug cable virtually connected to a physical debug port dedicated to a baseboard management controller;
emulating a first virtual debug device connected via the physical debug port dedicated to the baseboard management controller;
emulating a second virtual debug device connected via a universal serial bus interface to the baseboard management controller; and
bridging data passing during a debugging operation from the first virtual debug device through the baseboard management controller to the second virtual debug device.
16. The memory device of claim 15 , wherein the operations further comprise redirecting the data from the physical debug port to the second virtual debug device.
17. The memory device of claim 15 , wherein the operations further comprise redirecting the data from the first virtual debug device to the second virtual debug device.
18. The memory device of claim 15 , wherein the operations further comprise redirecting the data output from the physical debug port to an input at a universal serial bus hub controller.
19. The memory device of claim 15 , wherein the operations further comprise redirecting the data input at the physical debug port to an output a universal serial bus hub controller.
20. The memory device of claim 15 , wherein the operations further comprise establishing a physical interface with the physical debug port dedicated to the baseboard management controller.