Integrated metal gate CMOS devices
View Patent ↗A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
1. A semiconductor device comprising:
a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region;
a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region;
a first gate stack arranged on the first channel region, the first gate stack comprising:
a first metal layer arranged on the first channel region;
a work function metal layer arranged on the first metal layer; and
another work function metal arranged on the work function metal layer;
and
a second gate stack arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
2. The device of claim 1 , wherein the first gate stack further comprises a sacrificial patterning layer arranged on the work function metal layer.
3. The device of claim 1 , further comprising a third channel region.
4. The device of claim 3 , further comprising a fourth channel region.
5. The device of claim 4 , further comprising an interfacial layer on the first channel region, the second channel region, the third channel region, and the fourth channel region.
6. The device of claim 1 , wherein the substrate is doped.
7. The device of claim 1 , wherein the substrate is undoped.
8. The device of claim 1 , wherein the substrate includes doped regions.
9. The device of claim 1 , wherein the substrate includes doped regions and undoped regions.
10. The device of claim 5 , wherein the interfacial layer include SiO 2 .
11. The device of claim 5 , wherein the interfacial layer include SiN.
12. A semiconductor device comprising:
a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region;
a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region;
a first gate stack arranged on the first channel region, the first gate stack comprising:
a barrier metal layer arranged on the first channel region;
a first metal layer arranged on the barrier metal layer;
a work function metal layer arranged on the first metal layer; and
another work function metal arranged on the work function metal layer;
and
a second gate stack arranged on the second channel region, the second gate stack comprising:
a first metal layer arranged on the second channel region;
a sacrificial patterning layer arranged on the first metal layer;
a work function metal layer arranged on the second nitride layer; and
another work function metal arranged on the work function metal layer.
13. The device of claim 12 , wherein the first gate stack further comprises a sacrificial patterning layer arranged on the work function metal layer.
14. The device of claim 12 , wherein the second gate stack further comprises a third metal layer arranged on the work function metal layer.
15. The device of claim 12 , wherein the first metal layer includes TiN.
16. The device of claim 12 , further comprising a high k dielectric layer arranged on the first channel region and the second channel region.
17. The device of claim 12 , wherein the work function metal layer is selected from the group consisting of TiAl and Al.
18. The device of claim 12 , wherein the work function metal layer is selected from the group consisting of Ti, TiAlC, and TaAlC.
19. The device of claim 12 , further comprising an interfacial layer on the first channel region and the second channel region.
20. The device of claim 14 , further comprising a metal capping layer arranged on the first channel region.