Multiple string, multiple output digital to analog converter

1. A multiple output digital-to-analog converter (DAC) circuit providing at least two analog output signals of different resolution, the DAC circuit comprising:

a first string of first impedance elements;

a second string of second impedance elements coupled in parallel with the first string;

in response to a first digital input signal, a first switching network to couple a voltage produced across at least one of the first impedance elements across the second string to a first output node, the first digital input signal comprising a first digital bit stream having most significant bits (MSBs) and least significant bits (LSBs), the second impedance elements configured to produce a first analog signal corresponding to the first digital input signal; and

in response a second digital input signal, a second switching network to couple a voltage produced at one of the first impedance elements to a second output node, the first impedance elements configured to produce a second analog signal corresponding to the second digital input signal,

wherein the first output node and the second output node form multiple outputs.

2. The DAC circuit of claim 1 , the circuit comprising:

a loading compensation circuit to selectively adjust a pull-up or a pull-down of one of the first and second impedance elements to compensate for a loading by the other of the first and second impedance elements.

3. The DAC circuit of claim 2 , wherein the loading compensation circuit includes:

one or more anti-crosstalk impedance elements; and

a third switching network to couple the one or more anti-crosstalk impedance elements in parallel with at least one of the second impedance elements.

4. The DAC circuit of claim 2 , wherein the loading compensation circuit includes:

at least one current source; and

a third switching network to couple the at least one current source to the second string.

5. The DAC circuit of claim 2 , comprising:

a control circuit configured to control the loading compensation circuit using a comparison between the MSBs of the first digital input signal and the second digital input signal.

6. The DAC circuit of claim 1 , comprising:

a first multiplexer having a first input and a second input; and

a second multiplexer having a first input and a second input,

wherein the first input of the first multiplexer is coupled to the first output node and configured to receive the first analog signal,

wherein the first input of the second multiplexer is coupled to the second output node and configured to receive the second analog signal,

wherein the first input of the first multiplexer is coupled to the second input of the second multiplexer, and wherein the first input of the second multiplexer is coupled to the second input of the first multiplexer.

7. The DAC circuit of claim 1 , wherein the first impedance elements include first resistors, each of the first resistors having a first resistance, wherein the second impedance elements include second resistors, each of the second resistors having a second resistance.

8. The DAC circuit of claim 1 , comprising:

a fourth switching network to couple at least one of the second impedance elements to the first output node.

9. The DAC circuit of claim 1 , wherein the first output node is an output node of a first DAC, wherein the second output node is an output node of a second DAC, and wherein the first DAC and the second DAC share the first string.

10. A method of converting a first digital input string to a corresponding first analog signal having a first resolution and converting a second digital input string to a corresponding second analog signal having a second resolution, the method comprising:

providing a multiple output digital-to-analog converter (DAC) circuit, the DAC circuit comprising a first string of first impedance elements and a second string of second impedance elements coupled in parallel with the first string;

controlling, in response to a first digital input signal, a first switching network to couple a voltage produced across at least one of the first impedance elements across the second string to a first output node, the first digital input signal comprising a first digital bit stream having most significant bits (MSBs) and least significant bits (LSBs), the second impedance elements configured to produce a first analog signal corresponding to the first digital input signal; and

controlling, in response to a second digital input signal, a second switching network to couple a voltage produced at one of the first impedance elements to a second output node, the first impedance elements configured to produce a second analog signal corresponding to the second digital input signal, wherein the first output node and the second output node form multiple outputs.

11. The method of claim 10 , further comprising:

controlling a loading compensation circuit to selectively adjust a pull-up or a pull-down of one of the first and second impedance elements to compensate for a loading by the other of the first and second impedance elements.

12. The method of claim 1 , wherein controlling the loading compensation circuit comprises:

providing one or more anti-crosstalk impedance elements; and

controlling a third switching network to couple the one or more anti-crosstalk impedance elements in parallel with at least one of the second impedance elements.

13. The method of claim 11 , wherein controlling the loading compensation circuit comprises:

providing at least one current source; and

controlling a third switching network to couple the at least one current source to the second string.

14. The method of claim 11 , wherein controlling the loading compensation circuit comprises:

controlling the loading compensation circuit using a comparison between the MSBs of the first digital input signal and the second digital input signal.

15. The method of claim 10 , comprising:

controlling a fourth switching network to couple at least one of the second impedance elements to the first output node.

16. The method of claim 10 , comprising:

providing a first multiplexer having a first input and a second input; and

providing a second multiplexer having a first input and a second input,

wherein the first input of the first multiplexer is coupled to the first output node and configured to receive the first analog signal,

wherein the first input of the second multiplexer is coupled to the second output node and configured to receive the second analog signal,

wherein the first input of the first multiplexer is coupled to the second input of the second multiplexer, and wherein the first input of the second multiplexer is coupled to the second input of the first multiplexer; and

controlling the first and second multiplexers to output a pair of signals.

17. An electrochemical sensing circuit comprising:

a multiple output digital-to-analog converter (DAC) circuit providing at least two analog output signals of different resolution, the DAC circuit comprising:

a first string of first impedance elements;

a second string of second impedance elements;

in response to a first digital input signal, a first switching network to couple a voltage produced across at least one of the first impedance elements across the second string to a first output node, the first digital input signal comprising a first digital bit stream having most significant bits (MSBs) and least significant bits (LSBs), the second impedance elements configured to produce a first analog signal corresponding to the first digital input signal; and

in response a second digital input signal, a second switching network to couple a voltage produced at one of the first impedance elements to a second output node, the first impedance elements configured to produce a second analog signal corresponding to the second digital input signal,

wherein the first output node and the second output node form multiple outputs; and

an electrochemical sensor coupled to at least one of the first output node and the second output node.

18. The electrochemical sensing circuit of claim 17 , wherein the DAC circuit comprises:

a loading compensation circuit to selectively adjust a pull-up or a pull-down of one of the first and second impedance elements to compensate for a loading by the other of the first and second impedance elements.

19. The electrochemical sensing circuit of claim 18 , wherein the loading compensation circuit includes:

one or more anti-crosstalk impedance elements; and

a third switching network to couple the one or more anti-crosstalk impedance elements in parallel with at least one of the second impedance elements.

20. The electrochemical sensing circuit of claim 18 , wherein the loading compensation circuit includes:

at least one current source; and

a third switching network to couple the at least one current source to the second string.