Memory module and method system including the same

1. A memory module, comprising:

a front interface suitable for performing a serial-to-parallel conversion of a command, an address, and data that are received from a host memory controller;

a module controller suitable for communicating with the host memory controller through the front interface; and

a memory device suitable for operating in synchronization with a divided clock, receiving the command and the address from the module controller, and transferring and receiving data to and from the module controller once during one cycle of the divided clock,

wherein the number of lines for transferring the command, the address, and the data between the host memory controller and the front interface is greater than the number of lines for transferring the command, the address, and the data between the module controller and the memory device.

2. The memory module of claim 1 , wherein the module controller further performs an error correction operation.

3. The memory module of claim 1 , wherein the front interface further performs a parallel-to-serial conversion of the data that is to be transferred to the host memory controller.

4. The memory module of claim 3 , wherein an operation frequency of the module controller and an operation frequency of the memory device are 1/N of an operation frequency of the host memory controller, where N is an integer that is equal to or greater than 2.

5. The memory module of claim 4 , wherein the front interface performs a serial-to-parallel conversion in 1:N of the command and the address that are received from the host memory controller, and

wherein the number of the lines for transferring the command and the address between the module controller and the memory device is N times as many as the number of the lines for transferring the command and the address between the host memory controller and the front interface.

6. The memory module of claim 5 , wherein the front interface performs a serial-to-parallel conversion in 1:2N of the data that is received from the host memory controller, and performs a parallel-to-serial conversion in 2N:1 of the data that is transferred to the host memory controller, and

wherein the number of the lines for transferring the data between the module controller and the memory device is 2N times as many as the number of the lines for transferring the data between the host memory controller and the front interface.

7. The memory module of claim 4 , wherein the command, the address, and the data are transferred between the host memory controller and the front interface based on a DDR PHY Interface (DFI) standard interface.

8. The memory module of claim 7 , wherein N command signals of the same type among the command are transferred between the module controller and the memory device, and

N address signals of the same type among the address are transferred between the module controller and the memory device.

9. The memory module of claim 4 , wherein the front interface receives a clock from the host memory controller, divides a frequency of the clock into a 1/N frequency, and supplies the 1/N frequency to the module controller and the memory device.

10. The memory module of claim 1 , wherein the memory module is a Dual In-line Memory Module (DIMM).

11. A memory system, comprising:

a first command bus;

a first address bus;

a first data bus;

a host memory controller suitable for transferring a command through the first command bus, transferring an address through the first address bus, and transferring and receiving data through the first data bus;

a front interface suitable for performing a serial-to-parallel conversion of the command that is received through the first command bus, performing a serial-to-parallel conversion of the address that is received through the first address bus, performing a serial-to-parallel conversion of the data that is received through the first data bus, and performing a parallel-to-serial conversion of the data that is to be transferred through the first data bus to the host memory controller;

a module controller suitable for communicating with the host memory controller through the front interface;

a second command bus;

a second address bus;

a second data bus; and

a memory device suitable for operating in synchronization with a divided clock, receiving the command from the module controller through the second command bus, receiving the address from the module controller through the second address bus, and transferring and receiving the data to and from the module controller through the second data bus once during one cycle of the divided clock,

wherein the second command bus includes more transfer lines than the first command bus, the second address bus includes more transfer lines than the first address bus, and the second data bus includes more transfer lines than the first data bus.

12. The memory system of claim 11 , wherein the module controller further performs an error correction operation.

13. The memory system of claim 11 , wherein an operation frequency of the module controller and an operation frequency of the memory device are 1/N of an operation frequency of the host memory controller, where N is an integer that is equal to or greater than 2.

14. The memory system of claim 13 , wherein the front interface performs a serial-to-parallel conversion in 1:N of the command that is received through the first command bus and the address that is received through the first address bus, and

wherein the number of lines of the second command bus and the number of lines of the second address bus are N times as many as the number of lines of the first command bus and the number of lines of the first address bus.

15. The memory system of claim 14 , wherein the front interface performs a serial-to-parallel conversion in 1:2N of the data that is received through the first data bus, and performs a parallel-to-serial conversion in 2N:1 of the data that is transferred through the first command bus, and

wherein the number of lines of the second data bus is 2N times as many as the number of the lines of the first data bus.

16. The memory system of claim 13 , wherein N command signals of the same type among the command are transferred through the second command bus, and

N address signals of the same type among the address are transferred through the second address bus.

17. The memory system of claim 1 , wherein the front interface, the module controller, the second command bus, the second address bus, the second data bus, and the memory device are included in a memory module of a Dual In-line Memory Module (DIMM) type.

18. A memory system, comprising:

a first command bus;

a first address bus;

a plurality of first data buses;

a host memory controller suitable for transferring a command through the first command bus, transferring an address through the first address bus, and transferring and receiving data through the first data bus;

a front interface suitable for performing a serial-to-parallel conversion of the command that is received through the first command bus, performing a serial-to-parallel conversion of the address that is received through the first address bus, performing a serial-to-parallel conversion of the data that is received through the plurality of the first data buses, and performing a parallel-to-serial conversion of the data that is to be transferred through the plurality of the first data buses to the host memory controller;

a module controller suitable for communicating with the host memory controller through the front interface;

a second command bus;

a second address bus;

a plurality of second data buses that correspond to the plurality of the first data buses in 1:1; and

a plurality of memory devices suitable for operating in synchronization with a divided clock, receiving the command from the module controller through the second command bus, receiving the address from the module controller through the second address bus, and transferring and receiving the data to and from the module controller through a second data bus corresponding thereto among the plurality of the second data buses once during one cycle of the divided clock,

wherein the second command bus includes more transfer lines than the first command bus, the second address bus includes more transfer lines than the first address bus, and each of the plurality of the second data buses includes more transfer lines than each of the plurality of the first data buses.

19. The memory system of claim 18 , wherein the module controller further performs an error correction operation.

20. The memory system of claim 19 , further comprising:

an error correction code data bus; and

error correction code memory device,

wherein the error correction code memory device receives the command from the module controller through the second command bus, receives the address from the module controller through the second address bus, and transfers and receives an error correction code to and from the module controller through the error correction code data bus.