Semiconductor device
A semiconductor device includes a plurality of memory cells being disposed in a matrix in a memory cell array area, each of the memory cells includes a capacitive element including a cell plate electrode, a capacitive insulating film, and a storage node electrode, and a switch transistor coupled between the storage node electrode and a bit line and being controlled based on a potential of a word line, a peripheral circuit disposed in a peripheral circuit area adjacent to the memory cell array area, and a signal line formed at a boundary between the memory cell array area and the peripheral circuit area. The capacitive element has a cylinder shape. The storage node electrode is formed on inner wall of a hole which penetrates through a first insulating film layer and a second insulating film layer.
1. A semiconductor device, comprising:
a plurality of memory cells being disposed in a matrix in a memory cell array area, each of the memory cells including:
a capacitive element including a cell plate electrode, a capacitive insulating film, and a storage node electrode; and
a switch transistor coupled between the storage node electrode and a hit line and being controlled based on a potential of a word line;
a peripheral circuit disposed in a peripheral circuit area adjacent to the memory cell array area; and
a signal line formed at a boundary between the memory cell array area and the peripheral circuit area,
wherein the capacitive element has a cylinder shape, the storage node electrode being formed on an inner wall of a hole which penetrates through a first insulating film layer and a second insulating film layer, and
wherein the signal line is formed in at least one of the first insulating film layer and the second insulating film layer, and the signal line is supplied with a predetermined potential.
2. The semiconductor device according to claim 1 , wherein the signal line is arranged along an outer periphery of the memory cell array area.
3. The semiconductor device according to claim 1 , wherein the signal line is arranged along one side of the memory cell array area.
4. The semiconductor device according to claim 1 , further comprising:
in the memory cell array area, a plurality of dummy memory cells disposed along an outer periphery of the memory cell array area to surround the memory cells arranged in a matrix.
5. The semiconductor device according to claim 4 , wherein each of the dummy memory cells includes:
a capacitive element having a cylinder shape, and including a cell plate electrode and a storage node electrode; and
a switch transistor coupled to the capacitive element,
wherein the storage node electrode of said each of the dummy memory cells is formed on an inner wall of a hole which penetrates through the first insulating film layer and the second insulating film layer, and
wherein the cell plate electrode of said each of the dummy memory cells and the cell plate electrode of said each of the memory cells are connected to each other.
6. The semiconductor device according to claim 1 , wherein the predetermined potential includes a potential supplied to the cell plate electrode.
7. The semiconductor device according to claim 1 , wherein the peripheral circuit is provided to drive the memory cells.
8. The semiconductor device according to claim 1 , wherein the peripheral circuit comprises a sense amplifier circuit.
9. The semiconductor device according to claim 1 , wherein the peripheral circuit comprises a word line driver circuit.
10. The semiconductor device according to claim 1 , wherein the signal line includes a first signal line and the semiconductor device further comprises a second signal line,
wherein the first signal line and the second signal line are formed in the first insulating film layer and the second insulating film layer, respectively, and
wherein the first signal line and the second signal line are supplied with the predetermined potential.
11. A semiconductor device, comprising:
a plurality of memory cells being disposed in a matrix in a memory cell array area, each of the memory cells including:
a capacitive element including a storage node electrode coupled to a storage node; and
a switch transistor coupled between the storage node and a bit line and being controlled based on a potential of a word line;
a peripheral circuit disposed in a peripheral circuit area adjacent to the memory cell array area; and
a first signal line and a second signal line formed at a boundary between the memory cell array area and the peripheral circuit area,
wherein the capacitive element has a cylinder shape, the storage node electrode being formed on an inner wall of a hole which penetrates through a first insulating film layer and a second insulating film layer,
wherein the first signal line and the second signal line are formed in the first insulating film layer and the second insulating film layer, respectively, and
wherein the first signal line and the second signal line are respectively supplied with complementary potentials.
12. A semiconductor device, comprising:
a plurality of memory cells being disposed in a matrix in a memory cell array area, each of the memory cells including:
a capacitive element having a cylinder shape and including a cell plate electrode, a capacitive insulating film, and a storage node electrode, the storage node electrode being formed on an inner wall of a hole which penetrates through a plurality of insulating film layers; and
a switch transistor coupled between the storage node electrode and a bit line and being controlled based on a potential of a word line;
a peripheral circuit disposed in a peripheral circuit area adjacent to the memory cell array area; and
a plurality of signal lines formed at a boundary between the memory cell array area and the peripheral circuit area, the signal lines being formed in respectively different layers of the insulating film layers and being supplied with a predetermined potential.