IP Library Granted Patent US 10,241,764
Granted Patent B2
US 10,241,764 · App. 15/588,298 · Granted Mar 26, 2019

Automatically transform pass-by-value semantics into pass-by-reference implementation

Inventors: Hojin Kee (Austin, TX); David C. Uliana (Austin, TX); Tai A. Ly (Austin, TX); Adam T. Arnesen (Pflugerville, TX)
Assignee: National Instruments Corporation
G06F8/436G06F8/433G05B15/02
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Quick Facts
Patent No.
US 10,241,764
App. No.
15/588,298
Granted
Mar 26, 2019
Kind
B2
Abstract

System and method for compiling a program, including determining one or more program structures containing one or more variables at the entry and exit of each program structure, wherein each variable specifies a value transfer operation of one or more source variables to a destination variable between outside the program structure and inside the program structure. A subset of the destination variables may be determined for which assigning the destination variable to a memory resource of a corresponding source variable does not disrupt the functionality of the program. Implementation of the value transfer operations may be executable to map each of the determined subset of destination variables to a respective memory resource. The mapping may be dynamically changed, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

Claims (70)

1. An apparatus, comprising:

a processor; and

a non-transitory computer accessible memory medium coupled to the processor that stores program instructions executable by the apparatus to perform:

compiling a program to generate output code, the compiling comprising:

determining one or more program structures in the program containing one or more variables at the entry or exit of each of these program structures, wherein each variable at the entry or exit of a program structure specifies a value transfer between outside of a program structure and inside the program structure, and wherein each value transfer specifies a value transfer from one or more source variables to a destination variable; and

implementing each of the value transfer operations in the output code, wherein, during operation based on the output code, the implementation of the value transfer operation includes:

assigning each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources;

determining a subset of the destination variables for which assigning the destination variable to a memory resource of a corresponding source variable does not disrupt the functionality of the program; and

for the subset of the destination variables, dynamically changing the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

2. The apparatus of claim 1 ,

wherein said determining the subset of the destination variables comprises determining a memory resource requirement associated with the program.

3. The apparatus of claim 2 , wherein said compiling the program further comprises:

determining that the one or more program structures operate with a static schedule; and

in response to determining that the one or more program structures operate with a static schedule, collecting variables that transfer values across program structures into a group of related variables and analyzing the lifetimes of the related variables in the group of related variables.

4. The apparatus of claim 3 , wherein said compiling the program further comprises:

determining temporal overlap of the lifetimes of the related variables in the group of related variables; and

wherein said determining the subset of the destination variables is based on the determined temporal overlap of the lifetimes.

5. The apparatus of claim 2 , wherein said compiling the program further comprises:

determining that the one or more program structures operate with a dynamic schedule;

in response to determining that the one or more program structures operate with a dynamic schedule:

construct a segment dependency graph based on the one or more structures;

extract a segment conflict graph based on the segment dependency graph; and

determine the memory resource requirement associated with the program based on a maximum clique size of the segment conflict graph.

6. The apparatus of claim 1 , wherein the output code is configured for operation by a programmable hardware device.

7. A non-transitory computer accessible memory medium that stores program instructions executable by a functional unit to perform operations comprising:

compiling a program to generate output code, the compiling comprising:

determining one or more program structures in the program containing one or more variables at one or more of the entry and exit of each of these program structures, wherein each variable specifies a value transfer between outside of a program structure and inside the program structure, and wherein each value transfer specifies a value transfer from one or more source variables to a destination variable; and

implementing each of the value transfer operations in the output code, wherein, during operation based on the output code, the implementation of the value transfer operation includes:

assigning each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources;

determining a subset of the destination variables for which assigning the destination variable to a memory resource of a corresponding source variable does not disrupt the functionality of the program; and

for the determined subset of the destination variables, dynamically changing the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

8. The memory medium of claim 7 ,

wherein said determining the subset of the destination variables comprises determining a memory resource requirement associated with the program.

9. The memory medium of claim 8 , wherein said compiling the program further comprises:

in response to determining that the one or more program structures operate with a dynamic schedule:

constructing a segment dependency graph based on the one or more program structures;

extracting a segment conflict graph based on the segment dependency graph; and

determining the memory resource requirement associated with the program based on a maximum clique size of the segment conflict graph.

10. The memory medium of claim 7 , wherein said compiling the program further comprises:

determining that the one or more program structures operate with a static schedule; and

in response to determining that the one or more program structures operate with a static schedule, collecting variables that transfer values across program structures into a group of related variables and analyzing the lifetimes of the related variables in the group of related variables.

11. The memory medium of claim 10 , wherein said compiling the program further comprises:

determining temporal overlap of the lifetimes of the related variables in the group of related variables; and

wherein said determining the subset of the destination variables is based on the determined temporal overlap of the lifetimes.

12. The memory medium of claim 7 , wherein the output code is configured for programming a programmable hardware device to perform operations to implement the functionality of the program.

13. The memory medium of claim 7 , wherein said compiling allows operation of two or more program structures in a pipelined manner by passing values between the two or more program structures without copying values between their respective memory resources.

14. A method for compiling a program to generate output code, the method comprising:

by a processor:

determining one or more program structures in the program containing one or more variables at the entry or exit of each of these program structures, wherein each variable at the entry or exit of a program structure specifies a value transfer between outside of a program structure and inside the program structure, and wherein each value transfer specifies a value transfer from one or more source variables to a destination variable;

implementing each of the value transfer operations in the output code, wherein, during operation based on the output code, the implementation of the value transfer operation includes:

assigning each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources;

determining a subset of the destination variables for which assigning the destination variable to a memory resource of a corresponding source variable does not disrupt the functionality of the program; and

for the subset of the destination variables, dynamically changing the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

15. The method of claim 14 ,

wherein said determining the subset of the destination variables comprises determining a memory resource requirement associated with the program.

16. The method of claim 15 , wherein said compiling the program further comprises:

determining that the one or more program structures operate with a static schedule; and

in response to determining that the one or more program structures operate with a static schedule, collecting variables that transfer values across program structures into a group of related variables and analyzing the lifetimes of the related variables in the group of related variables.

17. The method of claim 16 , wherein said compiling the program further comprises:

determining temporal overlap of the lifetimes of the related variables in the group of related variables; and

wherein said determining the subset of the destination variables is based on the determined temporal overlap of the lifetimes.

18. The method of claim 15 , wherein said compiling the program further comprises:

determining that the one or more program structures operate with a dynamic schedule;

in response to determining that the one or more program structures operate with a dynamic schedule:

construct a segment dependency graph based on the one or more structures;

extract a segment conflict graph based on the segment dependency graph; and

determine the memory resource requirement associated with the program based on a maximum clique size of the segment conflict graph.

19. The method of claim 14 , the method further comprising:

programming a programmable hardware device based on the output code such that the programmable hardware device is configured to operate to perform the functionality.

20. The method of claim 14 , wherein said compiling allows operation of two or more program structures in a pipelined manner.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 057280/0028) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 065231/0466 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 052935/0001) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
Reel/Frame 065653/0463 →
SECURITY INTEREST Recorded Jun 18, 2021
From: NATIONAL INSTRUMENTS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 057280/0028 →
SECURITY INTEREST Recorded Jun 14, 2020
From: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052935/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2017
From: KEE, HOJIN; ULIANA, DAVID C.; LY, TAI A.; ARNESEN, ADAM T.
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 042259/0216 →
Continuity (1)
Related Publication 20180321925A1 · Nov 8, 2018