Method of manufacturing semiconductor device having a nonvolatile memory and a MISFET
Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.
1. A method of manufacturing a semiconductor device comprising a memory cell of a nonvolatile memory formed in a semiconductor substrate located in a first region, and a metal insulator semiconductor field effect transistor (MISFET) formed in the semiconductor substrate located in a second region,
the memory cell including a first gate electrode, and a second gate electrode which are formed over the semiconductor substrate to be adjacent to each other, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and a second gate insulating film formed between the second gate electrode and the semiconductor substrate and having a charge storage portion therein,
the MISFET including a third gate electrode formed over the semiconductor substrate, and a third gate insulating film formed between the third gate electrode and the semiconductor substrate, the method comprising the steps of:
(a) providing the semiconductor substrate;
(b) forming, over the semiconductor substrate located in the first region, the first gate electrode via the first gate insulating film, and the second gate electrode via the second gate insulating film;
(c) forming, over the semiconductor substrate, a first film so as to cover the first region and to expose the second region;
(d) after the step (c), forming a second film including a first conductive film over the first film in the first region and over the semiconductor substrate in the second region;
(e) patterning the second film to form a dummy gate electrode for forming the third gate electrode in the second region;
(f) after the step (e), removing the first film;
(g) after the step (f), forming, over the semiconductor substrate, a first insulating film so as to cover the first gate electrode, the second gate electrode, and the dummy gate electrode;
(h) polishing an upper surface of the first insulating film to expose the dummy gate electrode;
(i) after the step (h), removing at least one part of the dummy gate electrode; and
(j) embedding a second conductive film in a region from which the dummy gate electrode has been removed in the step (i) to form the third gate electrode,
wherein, in the step (c), an upper surface of the first film is higher than upper surfaces of the first and the second gate electrodes.
2. The method of manufacturing the semiconductor device according to claim 1 , wherein the first film comprises an insulating film.
3. The method of manufacturing the semiconductor device according to claim 1 ,
wherein the first conductive film has a first metal film, and a first silicon film over the first metal film, and
wherein the third gate electrode is a metal gate electrode.
4. The method of manufacturing the semiconductor device according to claim 3 further comprising, after the step (f) and prior to the step (g), the step of:
(g1) forming a semiconductor region for a source or drain of the memory cell in the semiconductor substrate located in the first region and forming a semiconductor region for a source or drain of the MISFET in the semiconductor substrate located in the second region.
5. The method of manufacturing the semiconductor device according to claim 3 , wherein the first metal film is a titanium nitride film.
6. The method of manufacturing the semiconductor device according to claim 3 ,
wherein, in the step (i), the first silicon film of the dummy gate electrode is removed, and
wherein, in the step (j), the first metal film that has formed the dummy gate electrode, and the second conductive film over the first metal film form the third gate electrode.
7. The method of manufacturing the semiconductor device according to claim 3 ,
wherein, in the step (i), the first silicon film of the dummy gate electrode and the first metal film thereof are removed, and
wherein, in the step (j), the second conductive film forms the third gate electrode.
8. The method of manufacturing the semiconductor device according to claim 1 , further comprising, after the step (d) and prior to the step (e), the step of:
(d1) removing a portion of the second film which covers the first gate electrode, the second gate electrode, and the first insulating film to leave the second film over the semiconductor substrate located in the second region.
9. The method of manufacturing the semiconductor device according to claim 1 ,
wherein the step (b) includes the steps of:
(b1) forming, over a main surface of the semiconductor substrate, a second insulating film for the first gate insulating film;
(b2) forming, over the second insulating film, a third conductive film for the first gate electrode;
(b3) patterning the third conductive film to form the first gate electrode in the first region;
(b4) forming, over the main surface of the semiconductor substrate, a third insulating film for the second gate insulating film so as to cover the first gate electrode;
(b5) forming, over the third insulating film, a fourth conductive film for the second gate electrode;
(b6) etching back the fourth conductive film to leave the fourth conductive film over a side wall of the first gate electrode via the third insulating film and thus form the second gate electrode; and
(b7) removing a portion of the third insulating film which is uncovered with the second gate electrode.
10. The method of manufacturing the semiconductor device according to claim 9 , wherein each of the third conductive film and the fourth conductive film is a silicon film.
11. The method of manufacturing the semiconductor device according to claim 9 ,
wherein, in the step (b3), the third conductive film is left in the second region, and
wherein, in the step (c), the first film is formed over the semiconductor substrate so as to cover the first gate electrode and the second gate electrode each located in the first region, and the third conductive film located in the second region,
the method further comprising, after the step (c) and prior to the step (d), the step of:
(c1) removing the third conductive film from the second region.
12. The method of manufacturing the semiconductor device according to claim 11 ,
wherein, in the step (b2), over the second insulating film, a first laminated film having the third conductive film, and a fourth insulating film over the second conductive film is formed,
wherein, in the step (b3), the first laminated film is patterned to form a laminated body including the first gate electrode in the first region, while the first laminated film remains in the second region,
wherein, in the step (b4), over the main surface of the semiconductor substrate, the third insulating film is formed so as to cover the laminated body,
wherein, in the step (b6), the fourth conductive film is etched back to remain the fourth conductive film over a side wall of the laminated body via the third insulating film and thus form the second gate electrode, and
wherein, in the step (c1), the first laminated film is removed from the second region.