IP Library Granted Patent US 10,425,050
Granted Patent B2
US 10,425,050 · App. 15/593,347 · Granted Sep 24, 2019

Amplification circuit, apparatus for amplifying, low noise amplifier, radio receiver, mobile terminal, base station, and method for amplifying

Inventors: Ashkan Naeini (Munich, DE); Robert Kostack (Dresden, DE); Herbert Stockinger (Schliersee, DE)
Assignee: Intel IP Corporation
H03F3/265H03F1/223H03F3/189H03F3/193H03H11/32H03F2200/294H03F2200/411
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Quick Facts
Patent No.
US 10,425,050
App. No.
15/593,347
Granted
Sep 24, 2019
Kind
B2
Abstract

Embodiments provide an amplification circuit, an apparatus for amplifying, a low noise amplifier, a radio receiver, a mobile terminal, a base station, and a method for amplifying. An amplification circuit ( 10 ) for amplifying a radio signal comprises a first amplification stage ( 12 ) configured to amplify an input signal, V in (t), to obtain an intermediate signal. The amplification circuit ( 10 ) further comprises a cascoding circuit ( 14 ) configured to amplify the intermediate signal to obtain a first output signal V outn (t). The amplification circuit ( 10 ) further comprises a second amplification stage ( 16 ) configured to amplify the intermediate signal to obtain a second output signal, V outp (t).

Claims (63)

1. An amplification circuit for amplifying a radio signal, comprising

a first amplification stage configured to amplify an input signal, V in (t), to generate an intermediate signal,

a cascoding circuit configured to amplify the intermediate signal to generate a first output signal V outn (t); and

a second amplification stage configured to amplify the intermediate signal to generate a second output signal, V outp (t);

wherein the first amplification stage comprises at least two MOSFETs, a first MOSFET, M 1N , of n-channel type and a second MOSFET, M 1P , of p-channel type,

the cascoding circuit comprises at least two MOSFETs, a first MOSFET, M 2N , of n-channel type and a second MOSFET, M 2P , of p-channel type,

each of the MOSFETs, M 1N , M 1P , M 2N , M 2P comprising at least a gate, a source and a drain connector,

a source connector of the first MOSFET, M 1N , of the first amplification stage is coupled to a negative power supply voltage or a reference potential,

a drain connector of the first MOSFET, M 1N , of the first amplification stage is coupled to a source connector of the first MOSFET, M 2N , of the cascoding circuit,

a drain connector of the first MOSFET, M 2N , of the cascoding circuit is coupled to a drain connector of the second MOSFET, M 2p , of the cascoding circuit,

a source connector of the second MOSFET, M 2p , of the cascoding circuit is coupled to a drain connector of the second MOSFET, M 1P , of the first amplification stage, and

a source connector of the second MOSFET, M 1P , of the first amplification stage is coupled to a positive power supply voltage,

wherein the input signal, V in (t), is coupled to the gate connectors of the first and second MOSFETs, M 1N and M 1P , of the first amplification stage, and wherein gate connectors of the first and second MOSFETs, M 2N and M 2P , of the cascoding circuit are coupled to a reference potential.

2. The amplification circuit of claim 1 , wherein the first and second output signals, V outn (t), V outp (t), form a differential output of the amplifier circuit.

3. The amplification circuit of claim 1 , wherein one of the first amplification stage and the second amplification stage is an inverting amplification stage and the other is a non-inverting amplification stage.

4. The amplification circuit of claim 1 , wherein the first amplification stage comprises a first push-pull stage cascoded with the cascoding circuit, and wherein the second amplification stage comprises a second push-pull stage configured to amplify the intermediate signal.

5. The amplification circuit of claim 1 , wherein the first amplification stage comprises at least two transistors, M 1N , M 1P , being coupled in a push-pull arrangement, and wherein the cascoding circuit comprises at least two transistors, M 2N , M 2P , being coupled in a push-pull arrangement between the at least two transistors, M 1N , M 1P , of the first amplification stage.

6. The amplification circuit of claim 5 , wherein the at least two transistors, M 1N , M 1P , of the first amplification stage are two MOSFETs, Metal-Oxide-Semiconductor Field-Effect Transistor, with different channel types.

7. The amplification circuit of claim 5 , wherein the at least two transistors, M 2N , M 2P , of the cascoding circuit are two MOSFETs with different channel types.

8. The amplification circuit of claim 5 , wherein a first transistor, M 1N , of the first amplification stage is coupled to a reference potential or negative power supply voltage and wherein a second transistor, M 1P , of the first amplification stage is coupled to a positive supply voltage.

9. The amplification circuit of claim 8 , wherein

a first transistor, M 2N , of the cascoding circuit is coupled to the first transistor, M 1N , of the first amplification stage,

the first transistor, M 2N , of the cascoding circuit is coupled to a second transistor, M 2P , of the cascoding circuit, and

the second transistor, M 2P , of the cascoding stage is coupled to the second transistor, M 1P , of the first amplification stage.

10. The amplification circuit of claim 1 , wherein the second amplification stage comprises a push-pull stage comprising at least two transistors, M 3N , M 3P .

11. The amplification circuit of claim 10 , wherein the at least two transistors, M 3N , M 3P , of the second amplification stage are two MOSFETs with different channel types.

12. The amplification circuit of claim 1 , wherein the at least two transistors, M 3N , M 3P , of the second amplification stage are coupled to each other in a push-pull arrangement, wherein a first transistor, M 3N , of the second amplification stage is coupled to a negative power supply voltage or a reference potential and wherein a second transistor, M 3P , of the second amplification stage is coupled to a positive power supply voltage.

13. The amplification circuit of claim 9 , wherein

the second amplification stage comprises a push-pull stage comprising two transistors, M 3N , M 3P ,

the two transistors, M 3N , M 3P , of the second amplification stage are coupled to each other in a push-pull arrangement,

a first transistor, M 3N , of the second amplification stage is coupled to a negative power supply voltage or a reference potential,

a second transistor, M 3P , of the second amplification stage is coupled to a positive power supply voltage,

the first transistor, M 3N , of the second amplification stage is coupled to the first transistor, M 1N , of the first amplification stage and to the first transistor, M 2N , of the cascoding circuit,

the second transistor, M 3P , of the second amplification stage is coupled to the second transistor, M 1P , of the first amplification stage and to the second transistor, M 2P , of the cascoding circuit.

14. The amplification circuit of claim 1 , wherein

the source connector of the first MOSFET, M 1N , of the first amplification stage is coupled to the negative power supply voltage or the reference potential through at least one resistor, R S1N ; and

the source connector of the second MOSFET, M 1P , of the first amplification stage is coupled to the positive power supply voltage through at least another resistor, R S1P .

15. The amplification circuit of claim 1 , wherein

the input signal is coupled to the gate connector of the first MOSFET, M 1N , of the first amplification stage through at least one capacitor, C 1N , and

the input signal is coupled to the gate connector of the second MOSFET, M 1P , of the first amplification stage through at least one other capacitor, C 1P .

16. The amplification circuit of claim 1 , wherein

the gate connector of the first MOSFET, M 2N , of the cascoding circuit is coupled to the reference potential through at least one capacitor, C 2N ; and

the gate connector of the second MOSFET, M 2P , of the cascoding circuit is coupled to the reference potential through at least one other capacitor, C 2P .

17. A low noise amplifier comprising the amplification circuit of claim 1 .

18. A radio receiver comprising the low noise amplifier of claim 17 .

19. A mobile terminal comprising the low noise amplifier of claim 17 .

20. A base station comprising the low noise amplifier of claim 17 .

21. The amplification circuit of claim 1 , wherein the first amplification stage comprises a push-pull stage cascoded with the cascoding circuit.

22. A method for amplifying a radio signal obtained at an input to provide an amplified signal at an output, comprising

amplifying an input signal, V in (t), with a first amplification stage, to generate an intermediate signal;

cascoding the intermediate signal, with a cascading circuit, to generate a first output signal, V outn (t);

amplifying the intermediate signal, with a second amplification stage, to generate a second output signal, V outp (t),

wherein amplifying the input signal comprises a cascoded push-pull stage,

wherein the first amplification stage comprises at least two MOSFETs, a first MOSFET, M 1N , of n-channel type and a second MOSFET, M 1P , of p-channel type,

the cascoding circuit comprises at least two MOSFETs, a first MOSFET, M 2N , of n-channel type and a second MOSFET, M 2P , of p-channel type,

each of the MOSFETs, M 1N , M 1P , M 2N , M 2P comprising at least a gate, a source and a drain connector,

a source connector of the first MOSFET, M 1N , of the first amplification stage is coupled to a negative power supply voltage or a reference potential,

a drain connector of the first MOSFET, M 1N , of the first amplification stage is coupled to a source connector of the first MOSFET, M 2N , of the cascoding circuit,

a drain connector of the first MOSFET, M 2N , of the cascoding circuit is coupled to a drain connector of the second MOSFET, M 2P , of the cascoding circuit,

a source connector of the second MOSFET, M 2P , of the cascoding circuit is coupled to a drain connector of the second MOSFET, M 1P , of the first amplification stage, and

a source connector of the second MOSFET, M 1P , of the first amplification stage is coupled to a positive power supply voltage,

wherein the input signal, V in (t), is coupled to the gate connectors of the first and second MOSFETs, M 1N and M 1P , of the first amplification stage, and wherein gate connectors of the first and second MOSFETs, M 2N and M 2P , of the cascoding circuit are coupled to a reference potential.

23. The method of claim 22 , wherein the first and second output signals, Voutn(t), Voutp(t), form a differential output of the amplifier circuit.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 053063/0205 →
CONFIRMATORY ASSIGNMENT Recorded Jun 25, 2020
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 053051/0016 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2017
From: NAEINI, ASHKAN; KOSTACK, ROBERT; STOCKINGER, HERBERT
To: INTEL IP CORPORATION
Reel/Frame 042348/0619 →
Priority Claims (1)
EP 16174226 · Jun 13, 2016 · regional
Continuity (1)
Related Publication 20170359040A1 · Dec 14, 2017