IP Library Granted Patent US 10,609,401
Granted Patent B2
US 10,609,401 · App. 15/594,173 · Granted Mar 31, 2020

Device and method for block compression and block decompression

Inventors: Hirobumi Furihata (Tokyo, JP); Masao Orio (Tokyo, JP)
Assignee: Synaptics Japan GK
H04N19/426H04N19/124H04N19/176
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Quick Facts
Patent No.
US 10,609,401
App. No.
15/594,173
Granted
Mar 31, 2020
Kind
B2
Abstract

An image compression device includes: a first compression processing circuit configured to generate a first compressed image data by performing a first block compression process on an image data and a dither value generator circuit. When the first compressed image data associated with a compression target block is generated, the dither value generator circuit is configured to generate at least one dither value in response to block coordinates indicating a position of the compression target block in an image and the first compression processing circuit is configured to perform a quantization process using the at least one dither value in the first block compression process.

Claims (72)

1. An image compression device, comprising:

a first compression processing circuit configured to generate compressed image data by performing a block compression process on image data comprising grayscale values for a plurality of pixels; and

a dither value generator circuit configured to:

generate first dither values for a first compression target block at least partially based on first block coordinates indicating a horizontal and vertical position of the first compression target block within an image corresponding to the image data when first compressed image data of the compressed image data associated with the first compression target block is generated, wherein the first compression target block corresponds to a first two or more pixels of the plurality of pixels; and

generate second dither values for a second compression target block at least partially based on second block coordinates indicating a horizontal and vertical position of the second compression target block within the image when second compressed image data of the compressed image data associated with the second compression target block is generated, wherein the second compression target block corresponds to a second two or more pixels of the plurality of pixels and the horizontal and vertical position of the second compression target block is different from the horizontal and vertical position of the first compression target block, and

wherein the first compression processing circuit is further configured to perform a first quantization process using the first dither values and the second dither values in the block compression process.

2. The image compression device according to claim 1 , wherein the first dither values include a plurality of dither values associated with respective pixels of the first compression target block, wherein the dither value generator circuit is configured to generate pseudo-random numbers using as seed values coordinates of the respective pixels obtained from the first block coordinates and generate the first dither values associated with the respective pixels from the pseudo-random numbers.

3. The image compression device according to claim 1 , further comprising:

second to N th compression processing circuits configured to generate second to N th compressed image data by performing second to N th block compression processes on the image data, respectively, N being an integer of three or more; and

a compressed data selection circuit configured to output a selected one of the second to N th compressed image data as an output compressed image data,

wherein the second to N th block compression processes are different from each other, and

wherein the second to N th compression processing circuits are configured to each perform a second quantization process using at least one of the first dither values and the second dither values in the second to N th block compression processes, respectively.

4. The image compression device according to claim 3 , wherein the output compressed image data is selected from the second to N th compressed image data in response to a feature of the image data of at least one of the first compression target block and the second compression target block.

5. An image decompression circuit, comprising:

a first decompression processing circuit configured to generate decompressed image data by performing a first decompression process on compressed image data generated through a block compression process, wherein the decompressed image data comprises grayscale values for a plurality of pixels; and

a dither value generator circuit configured to:

generate first dither values for a first decompression target block at least partially based on first block coordinates indicating a horizontal and vertical position of the first decompression target block in an image corresponding to the decompressed imaqe data when first decompressed image data of the decompressed image data associated with the first decompression target block is generated, wherein the first decompression target block corresponds to a first two or more pixels of the plurality of pixels; and

generate second dither values for a second decompression target block at least partially based on second block coordinates indicating a horizontal and vertical position of the second decompression target block in the imaqe when second decompressed image data of the decompressed image data associated with the second decompressed target block is generated, wherein the second decompression target block corresponds to a second two or more pixels of the plurality of pixels and the horizontal and vertical position of the second decompression target block is different from the horizontal and vertical position of the first decompression target block, and

wherein the first decompression processing circuit is further configured to perform a first inverse quantization process using at least one of the first dither values and the second dither values in the first decompression process.

6. The image decompression circuit according to claim 5 , wherein the first dither values includes a plurality of dither values associated with respective pixels of the first decompression target block,

wherein the dither value generator circuit is configured to generate pseudo-random numbers using as seed values coordinates of the respective pixels obtained from the first block coordinates and generate the first dither values associated with the respective pixels from the pseudo-random numbers.

7. The image decompression circuit according to claim 5 , further comprising:

second to N th decompression processing circuits configured to generate second to N th decompressed image data by performing second to N th block decompression processes on the compressed image data, respectively, N being an integer of three or more; and

a decompressed data selection circuit configured to output a selected one of the second to N th decompressed image data as an output decompressed image data,

wherein the second to N th decompression processes are different from each other, and

wherein the second to N th decompression processing circuits are configured to each perform a second inverse quantization process using at least one of the first dither values and the second dither values in the second to N th decompression processes, respectively.

8. An image compression and decompression system, comprising:

block compression circuitry configured to generate compressed image data by performing a block compression process on image data comprising grayscale values for a plurality of pixels; and

block decompression circuitry configured to generate a decompressed image data by performing a decompression process adapted to the block compression process on the compressed image data,

wherein, when the compressed image data associated with a first compression target block and a second compression target block is generated, the block compression circuitry is configured to:

generate first dither values for the first compression target block at least partially based on first block coordinates indicating a horizontal and vertical position of the first compression target block in a first image corresponding to the image data, wherein the first compression target block corresponds to a first two or more pixels of the plurality of pixels;

generate second dither values for the second compression target block at least partially based on second block coordinates indicating a horizontal and vertical position of the second compression target block in the first image, wherein the second compression target block corresponds to a second two or more pixels of the plurality of pixels and the horizontal and vertical position of the second compression target block is different from the horizontal and vertical position of the first compression target block; and

perform a quantization process using the first dither values and the second dither values, and

wherein, when the decompressed image data associated with a decompression target block is generated, the block decompression circuitry is configured to generate third dither values based on third block coordinates indicating a position of the decompression target block in a second image and perform an inverse quantization process using the third dither values.

9. The image compression and decompression system of claim 8 , wherein the first dither values include a plurality of dither values associated with respective pixels of the first compression target block, wherein the block compression circuitry is configured to generate pseudo-random numbers using as seed values coordinates of the respective pixels obtained from the first block coordinates and generate the first dither values associated with the respective pixels from the pseudo-random numbers.

10. The image compression and decompression system of claim 8 , further comprising:

second to N th compression processing circuits configured to generate second to N th compressed image data by performing second to N th block compression processes on the image data, respectively, N being an integer of three or more; and

a compressed data selection circuit configured to output a selected one of the second to N th compressed image data as an output compressed image data,

wherein the second to N th block compression processes are different from each other, and

wherein the second to N th compression processing circuits are configured to each perform a second quantization process using at least one of the first dither values and the second dither values in the second to N th block compression processes, respectively.

11. The image compression and decompression system of claim 10 , wherein the output compressed image data is selected from the second to N th compressed image data in response to a feature of the image data of at least one of the first compression target block and the second compression target block.

12. A display driver for driving a display panel, comprising:

block compression circuitry configured to generate compressed image data by performing a block compression process on image data comprising grayscale values for a plurality of pixels;

a display memory storing the compressed image data;

block decompression circuitry configured to generate a decompressed image data by performing a decompression process adapted to the block compression process on the compressed image data read out from the display memory; and

drive circuitry configured to drive the display panel in response to the decompressed image data,

wherein, when the compressed image data associated with a first compression target block and a second compression target block is generated, the block compression circuitry is configured to:

generate first dither values for the first compression target block at least partially based on first block coordinates indicating a horizontal and vertical position of the first compression target block in a first image, wherein the first compression target block corresponds to a first two or more pixels of the plurality of pixels;

generate second dither values for the second compression target block at least partially based on second block coordinates indicating a horizontal and vertical position of the second compression target block in the first image, wherein the second compression target block corresponds to a second two or more pixels of the plurality of pixels and the horizontal and vertical position of the second compression target block is different from the horizontal and vertical position of the first compression target block; and

perform a quantization process using the first dither values and the second dither values, and

wherein, when the decompressed image data associated with a decompression target block is generated, the block decompression circuitry is configured to generate third dither values based on third block coordinates indicating a horizontal and vertical position of the decompression target block in a second image and perform an inverse quantization process using the third dither values.

13. The display driver of claim 12 , wherein the first dither values include a plurality of dither values associated with respective pixels of the first compression target block, wherein the block compression circuitry is further configured to generate pseudo-random numbers using as seed values coordinates of the respective pixels obtained from the first block coordinates and generate the first dither values associated with the respective pixels from the pseudo-random numbers.

14. The display driver of claim 12 , further comprising:

second to N th compression processing circuits configured to generate second to N th compressed image data by performing second to N th block compression processes on the image data, respectively, N being an integer of three or more; and

a compressed data selection circuit configured to output a selected one of the second to N th compressed image data as an output compressed image data,

wherein the second to N th block compression processes are different from each other, and

wherein the second to N th compression processing circuits are configured to each perform a second quantization process using at least one of the first dither values and the second dither values in the second to N th block compression processes, respectively.

15. The display driver of claim 14 , wherein the output compressed image data is selected from the second to N th compressed image data in response to a feature of the image data of at least one of the first compression target block and the second compression target block.

16. A display driver for driving a display panel, comprising:

a decompression processing circuit configured to generate a decompressed image data by performing a decompression process on a compressed image data generated through a block compression process, the decompressed image data comprises grayscale values for a plurality of pixels;

drive circuitry driving the display panel in response to the decompressed image data; and

a dither value generator circuit configured to:

generate first dither values for a first decompression target block at least partially based on first block coordinates indicating a horizontal and vertical position of the first decompression target block within an image corresponding to the decompressed image data when first decompressed image data of the decompressed image data associated with the first decompression target block is generated, wherein the first decompression target block corresponds to a first two or more pixels of the plurality of pixels; and

generate second dither values for a second decompression target block at least partially based on second block coordinates indicating a horizontal and vertical position of the second decompression target block within the image when second decompression image data of the decompressed image data associated with the second decompressed target block is generated, wherein the second decompression target block corresponds to a second two or more pixels of the plurality of pixels and the horizontal and vertical position of the second decompression target block is different from the horizontal and vertical position of the first decompression target block, and

wherein the decompression processing circuit is further configured to perform an inverse quantization process using at least one of the first dither values and the second dither values in the decompression process.

17. The display driver of claim 16 , wherein the first dither values a plurality of dither values associated with respective pixels of the decompression target block,

wherein the dither value generator circuit is configured to generate pseudo-random numbers using as seed values coordinates of the respective pixels obtained from the first block coordinates and generate the first dither values associated with the respective pixels from the pseudo-random numbers.

18. The display driver of claim 16 , further comprising:

second to N th decompression processing circuits configured to generate second to N th decompressed image data by performing second to N th block decompression processes on the compressed image data, respectively, N being an integer of three or more; and

a decompressed data selection circuit configured to output a selected one of the second to N th decompressed image data as an output decompressed image data,

wherein the second to N th decompression processes are different from each other, and

wherein the second to N th decompression processing circuits are configured to each perform a second inverse quantization process using at least one of the first dither values and the second dither values in the second to N th decompression processes, respectively.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2024
From: SYNAPTICS JAPAN GK
To: SYNAPTICS INCORPORATED
Reel/Frame 067793/0211 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 051316 FRAME: 0777. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 18, 2020
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052186/0756 →
SECURITY INTEREST Recorded Dec 16, 2019
From: SYNAPTICS INCORPROATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 051316/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2017
From: FURIHATA, HIROBUMI; ORIO, MASAO
To: SYNAPTICS DISPLAY DEVICES GK
Reel/Frame 042364/0091 →
CHANGE OF NAME Recorded May 12, 2017
From: SYNAPTICS DISPLAY DEVICES GK
To: SYNAPTICS JAPAN GK
Reel/Frame 042364/0107 →
Priority Claims (1)
JP 2016-096958 · May 13, 2016 · national
Continuity (1)
Related Publication 20170332090A1 · Nov 16, 2017