Compressed data transmission in panel display system

1. A display system, comprising:

a display panel;

a host device; and

a display driver driving the display panel,

wherein the host device is configured to divide original data respectively associated with subpixels of pixels of the display panel into first to N th stream data for N being an integer of two or more, generate first to N th compressed stream data by compressing the first to N th stream data through a variable length compression, respectively, individually divide each of the first to N th compressed stream data into fixed-length blocks, sort the fixed-length blocks, and sequentially transmit the sorted fixed-length blocks to the display driver,

wherein the display driver includes:

a memory storing the fixed-length blocks sequentially received from the host device;

a decompression circuitry reading out the fixed-length blocks from the memory and generating decompressed data by performing a decompression process on the fixed-length blocks read out to generate decompressed data; and

a drive circuitry driving the subpixels of the pixels of the display panel in response to the decompressed data,

wherein the decompression circuitry includes:

first to N th processing circuits; and

a state controller reading out the fixed-length blocks from the memory in response to requests from the first to N th processing circuits and delivering the fixed-length blocks to the first to N th processing circuit,

wherein the first to N th processing circuits each perform a predetermined process on the fixed-length blocks received from the state controller to generate processed data,

wherein the decompressed data include the processed data output from the first to N th processing circuits, and

wherein the host device is configured to sort the fixed-length blocks so that the fixed-length blocks are supplied to the memory in an order in which the first to N th processing circuits require the fixed-length blocks to the state controller.

2. The display system according to claim 1 , wherein the host device determines an order in which the fixed-length blocks are sorted, through performing with software a process same as that performed on the fixed-length blocks by the state controller and the first to N th processing circuits.

3. The display system according to claim 1 , wherein the fixed-length blocks are supplied from the memory to the decompression circuitry in an order in which the fixed-length blocks are supplied from the host device to the memory.

4. The display system according to claim 1 , wherein the original data include correction data defined for the respective subpixels of the pixels,

wherein the decompressed data include decompressed correction data corresponding to the correction data,

wherein the host device transmits image data specifying grayscale values of the respective subpixels of the pixels to the display driver,

wherein the display driver further includes a correction calculation circuitry correcting the image data in response to the decompressed correction data to generate corrected image data,

wherein the correction calculation circuitry is configured to generate the corrected image data associated with a certain subpixel of a certain pixel by correcting the image data associated with the certain subpixel of the certain pixel in response to the decompressed correction data associated with the certain subpixel of the certain pixel, and

wherein the drive circuitry drives the subpixels of the pixels of the display panel, in response to the corrected image data.

5. The display system according to claim 1 , wherein the original data include original image data specifying grayscale values of the respective subpixels of the pixels,

wherein the decompressed data include decompressed image data corresponding to the original image data, and

wherein the drive circuitry drives the subpixels of the pixels of the display panel in response to the decompressed image data.

6. The display system according to claim 1 , wherein the display driver includes a correction calculation circuitry,

wherein, when the display system is placed in a first operation mode, the original data include original image data specifying grayscale values of the respective subpixels of the pixels, the decompressed data include decompressed image data corresponding to the original image data and the drive circuitry drives the subpixels of the pixels of the display panel in response to the decompressed image data,

wherein, when the display system is placed in a second operation mode, the original data include correction data defined for the respective subpixels of the pixels, the decompressed data include decompressed correction data corresponding to the correction data, the host device transmits image data specifying grayscale values of the respective subpixels of the pixels to the display driver, the correction calculation circuitry generates corrected image data by correcting the image data in response to the decompressed correction data, and the drive circuitry drives the subpixels of the pixels of the display panel in response to the corrected image data, and

wherein, in the second operation mode, the corrected image data associated with a certain subpixel of a certain pixel is generated by correcting the image data associated with the certain subpixel of the certain pixel in response to the decompressed correction data associated with the certain subpixel of the certain pixel.

7. The display system according to claim 2 , wherein the original data include correction data defined for each of the subpixels of the pixels,

wherein the decompressed data include decompressed correction data corresponding to the correction data,

wherein the host device transmits image data specifying grayscale values of the respective subpixels of the pixels to the display driver,

wherein the display driver further includes a correction calculation circuitry generating corrected image data by correcting the image data in response to the decompressed correction data,

wherein the correction calculation circuitry is configured to generate the corrected image data associate with a certain subpixel of a certain pixel by correcting the image data associated with the certain subpixel of the certain pixel in response to the decompressed correction data associated with the certain subpixel of the certain pixel, and

wherein the drive circuitry drives the subpixels of the pixels of the display panel in response to the corrected image data.

8. The display system according to claim 2 , wherein the original data include original image data specifying grayscale values of the respective subpixels of the pixels,

wherein the decompressed data include decompressed image data corresponding to the original image data, and

wherein the drive circuitry drives the subpixels of the pixels of the display panel in response the decompressed image data.

9. The display system according to claim 2 , wherein the display driver includes a correction calculation circuitry,

wherein, when the display system is placed in a first operation mode, the original data include original image data specifying grayscale values of the respective subpixels of the pixels, the decompressed data include decompressed image data corresponding to the original image data and the drive circuitry drives the subpixels of the pixels of the display panel in response to the decompressed image data,

wherein, when the display system is placed in a second operation mode, the original data include correction data defined for the respective subpixels of the pixels, the decompressed data include decompressed correction data corresponding to the correction data, the host device transmits image data specifying grayscale values of the respective subpixels of the pixels to the display driver, the correction calculation circuit generates the corrected image data by correcting the image data in response to the decompressed correction data, and the drive circuitry drives the subpixels of the pixels of the display panel in response to the corrected image data, and

wherein, in the second operation mode, the corrected image data associated with a certain subpixel of a certain pixel is generated by correcting the image data associated with the certain subpixel of the certain pixel in response to the decompressed correction data associated with the certain subpixel of the certain pixel.

10. The display system according to claim 3 , wherein the original data include correction data defined for the respective subpixels of the pixels,

wherein the decompressed data include decompressed correction data corresponding to the correction data,

wherein the host device transmits image data specifying grayscale values of the respective subpixels of the pixels to the display driver,

wherein the display driver further includes a correction calculation circuitry generating corrected image data by correcting the image data in response to the decompressed correction data,

wherein the correction calculation circuitry is configured to generate the corrected image data associated with a certain subpixel of a certain pixel by correcting the image data associated with the certain subpixel of the certain pixel in response to the decompressed correction data associated with the certain subpixel of the certain pixel, and

wherein the drive circuitry drives the subpixels of the pixels of the display panel in response to the corrected image data.

11. The display system according to claim 3 , wherein the original data include original image data specifying grayscale values of the respective subpixels of the pixels,

wherein the decompressed data include decompressed image data corresponding to the original image data, and

wherein the drive circuitry drives the subpixels of the pixels of the display panel in response to the decompressed image data.

12. The display system according to claim 3 , wherein the display driver includes correction calculation circuitry,

wherein, when the display system is placed in a first operation mode, the original data include original image data specifying grayscale values of the respective subpixels of the pixels, the decompressed data include decompressed image data corresponding to the original image data and the drive circuitry drives the subpixels of the pixels of the display panel in response to the decompressed image data,

wherein, when the display system is placed in a second operation mode, the original data include correction data defined for the respective subpixels of the pixels, the decompressed data include decompressed correction data corresponding to the correction data, the host device transmits image data specifying grayscale values of the respective subpixels of the pixels to the display driver, the correction calculation circuit generates the corrected image data by correcting the image data in response to the decompressed correction data, and the drive circuitry drives the subpixels of the pixels of the display panel in response to the corrected image data, and

wherein, in the second operation mode, the corrected image data associated with a certain subpixel of a certain pixel is generated by correcting the image data associated with the certain subpixel of the certain pixel in response to the decompressed correction data associated with the certain subpixel of the certain pixel.

13. A host device to be used in a display system including a display driver driving a display panel, the device comprising:

a storage device which stores compression software; and

a processor which executes the compression software,

wherein the processor is programmed with the compression software to divide original data respectively associated with subpixels of pixels of the display panel into first to N th stream data for N being an integer of two or more, generate first to N th compressed stream data by compressing the first to N th stream data through a variable length compression, respectively, individually divide each of the first to N th compressed stream data into fixed-length blocks, sort the fixed-length blocks, and sequentially transmit the sorted fixed-length blocks to the display driver,

wherein the display driver includes:

a memory storing the fixed-length blocks sequentially received from the host device,

a decompression circuitry reading out the fixed-length blocks from the memory and generating decompressed data by performing a decompression process on the fixed-length blocks read out to generate decompressed data, and

a drive circuitry driving the subpixels of the pixels of the display panel in response to the decompressed data,

wherein the decompression circuitry includes:

first to N th processing circuits; and

a state controller reading out the fixed-length blocks from the memory in response to requests from the first to N th processing circuits and delivering the fixed-length blocks to the first to N th processing circuit,

wherein the first to N th processing circuits each perform a predetermined process on the fixed-length blocks received from the state controller to generate processed data,

wherein the decompressed data include the processed data output from the first to N th processing circuits, and

wherein the processor is programmed with the compression software to sort the fixed-length blocks so that the fixed-length blocks are supplied to the memory in an order in which the first to N th processing circuits require the fixed-length blocks to the state controller.

14. The host device according to claim 13 , wherein the processor is programmed to determine an order in which the fixed-length blocks are sorted, through performing with software a process same as that performed on the fixed-length blocks by the state controller and the first to N th processing circuits.

15. A non-transitory storage medium storing a program when executed causes a host device included in a display system including a display driver driving a display panel to perform the following steps of:

dividing original data respectively associated with subpixels of pixels of the display panel into first to N th stream data for N being an integer of two or more;

generating first to N th compressed stream data by compressing the first to N th stream data through a variable length compression, respectively;

individually dividing each of the first to N th compressed stream data into fixed-length blocks;

sorting the fixed-length blocks of the first to N th stream data and sequentially transmitting the sorted fixed-length blocks to the display driver,

wherein the display driver includes:

a memory storing the fixed-length blocks sequentially received from the host device,

a decompression circuitry reading out the fixed-length blocks from the memory and generating decompressed data by performing a decompression process of the fixed-length blocks read out to generate decompressed data, and

a drive circuitry driving the subpixels of the pixels of the display panel in response to the decompressed data,

wherein the decompression circuitry includes:

first to N th processing circuits; and

a state controller reading out the fixed-length blocks from the memory in response to requests from the first to N th processing circuits and delivering the fixed-length blocks to the first to N th processing circuit,

wherein the first to N th processing circuits each perform a predetermined process on the fixed-length blocks received from the state controller to generate processed data,

wherein the decompressed data include the processed data output from the first to N th processing circuits, and

wherein, in the step of sequentially transmitting the sorted fixed-length blocks to the display driver, the fixed-length blocks are sorted so that the fixed-length blocks are supplied to the memory in an order in which the first to N th processing circuits require the fixed-length blocks to the state controller.

16. The non-transitory storage medium according to claim 15 , wherein when executed the program further causes the host device to determine an order in which the fixed-length blocks are sorted, through performing with software a process same as that performed on the fixed-length blocks by the state controller and the first to N th processing circuits.